From fd2963cae60c87aa3bcf382829cb7c44e6e0c2ae Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Tue, 1 Jan 2019 14:48:54 +0100 Subject: Fix linting warnings --- src/Test/VeriFuzz/Graph/ASTGen.hs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/Test/VeriFuzz/Graph/ASTGen.hs') diff --git a/src/Test/VeriFuzz/Graph/ASTGen.hs b/src/Test/VeriFuzz/Graph/ASTGen.hs index 2a82592..00ec88b 100644 --- a/src/Test/VeriFuzz/Graph/ASTGen.hs +++ b/src/Test/VeriFuzz/Graph/ASTGen.hs @@ -42,7 +42,7 @@ outputsC c = genPortsAST :: (Circuit -> [Node]) -> Circuit -> [Port] genPortsAST f c = - (port . frNode <$> f c) + port . frNode <$> f c where port = Port Wire 1 @@ -50,7 +50,7 @@ genPortsAST f c = -- assignment expressions. genAssignExpr :: Gate -> [Node] -> Maybe Expr genAssignExpr g [] = Nothing -genAssignExpr g (n:[]) = Just . Id $ frNode n +genAssignExpr g [n] = Just . Id $ frNode n genAssignExpr g (n:ns) = BinOp wire op <$> genAssignExpr g ns where wire = Id $ frNode n -- cgit