From 2de15f8f32d48b09a9a2c92c25b6b0b3bb4492e0 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Sun, 30 Dec 2018 12:03:35 +0100
Subject: [Fix #14] Add size to Port type

---
 src/Test/VeriFuzz/Graph/ASTGen.hs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/Test/VeriFuzz/Graph')

diff --git a/src/Test/VeriFuzz/Graph/ASTGen.hs b/src/Test/VeriFuzz/Graph/ASTGen.hs
index 00eb71d..cf996de 100644
--- a/src/Test/VeriFuzz/Graph/ASTGen.hs
+++ b/src/Test/VeriFuzz/Graph/ASTGen.hs
@@ -44,7 +44,7 @@ genPortsAST :: (Circuit -> [Node]) -> Circuit -> [Port]
 genPortsAST f c =
   (port . frNode <$> f c)
   where
-    port = Port $ PortNet Wire
+    port = Port (PortNet Wire) 1
 
 -- | Generates the nested expression AST, so that it can then generate the
 -- assignment expressions.
@@ -77,7 +77,7 @@ genModuleDeclAST c = ModDecl id output ports items
   where
     id = Identifier "gen_module"
     ports = genPortsAST inputsC c
-    output = Just $ Port (PortNet Wire) "y"
+    output = Just $ Port (PortNet Wire) 1 "y"
     items = genAssignAST c
 
 generateAST :: Circuit -> VerilogSrc
-- 
cgit