From b679d2c6b19f647a3af98019426dfd05e8e103e9 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Mon, 31 Dec 2018 13:06:56 +0100
Subject: Finish module instantiation

---
 src/Test/VeriFuzz/Verilog/AST.hs | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'src/Test/VeriFuzz/Verilog/AST.hs')

diff --git a/src/Test/VeriFuzz/Verilog/AST.hs b/src/Test/VeriFuzz/Verilog/AST.hs
index 3ae595f..85c3e99 100644
--- a/src/Test/VeriFuzz/Verilog/AST.hs
+++ b/src/Test/VeriFuzz/Verilog/AST.hs
@@ -385,6 +385,12 @@ instance QC.Arbitrary VerilogSrc where
 instance IsString Identifier where
   fromString = Identifier . T.pack
 
+instance Semigroup Identifier where
+  (Identifier a) <> (Identifier b) = Identifier (a <> b)
+
+instance Monoid Identifier where
+  mempty = Identifier mempty
+
 -- Traversal Instance
 
 traverseExpr :: Traversal' Expression Expression
-- 
cgit