From 4b29933ce947acb9da6fb1d3a61aae186e235843 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Mon, 31 Dec 2018 19:17:04 +0100
Subject: Remove sep and fromList in favour of fold

---
 src/Test/VeriFuzz/Verilog/CodeGen.hs | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'src/Test/VeriFuzz/Verilog/CodeGen.hs')

diff --git a/src/Test/VeriFuzz/Verilog/CodeGen.hs b/src/Test/VeriFuzz/Verilog/CodeGen.hs
index 9e99f70..4fecaec 100644
--- a/src/Test/VeriFuzz/Verilog/CodeGen.hs
+++ b/src/Test/VeriFuzz/Verilog/CodeGen.hs
@@ -33,7 +33,7 @@ defMap stat = fromMaybe ";\n" $ genStmnt <$> stat
 -- | Convert the 'VerilogSrc' type to 'Text' so that it can be rendered.
 genVerilogSrc :: VerilogSrc -> Text
 genVerilogSrc source =
-  fromList $ genDescription <$> source ^. getVerilogSrc
+  fold $ genDescription <$> source ^. getVerilogSrc
 
 -- | Generate the 'Description' to 'Text'.
 genDescription :: Description -> Text
@@ -51,7 +51,7 @@ genModuleDecl mod =
     ports
       | noIn && noOut = ""
       | otherwise = "(" <> (comma $ genModPort <$> outIn) <> ")"
-    modItems = fromList $ genModuleItem <$> mod ^. moduleItems
+    modItems = fold $ genModuleItem <$> mod ^. moduleItems
     noOut = null $ mod ^. modOutPorts
     noIn = null $ mod ^. modInPorts
     outIn = (mod ^. modOutPorts) ++ (mod ^. modInPorts)
@@ -182,7 +182,7 @@ genStmnt :: Stmnt -> Text
 genStmnt (TimeCtrl d stat) = genDelay d <> " " <> defMap stat
 genStmnt (EventCtrl e stat) = genEvent e <> " " <> defMap stat
 genStmnt (SeqBlock s) =
-  "begin\n" <> fromList (genStmnt <$> s) <> "end\n"
+  "begin\n" <> fold (genStmnt <$> s) <> "end\n"
 genStmnt (BlockAssign a) = genAssign " = " a <> ";\n"
 genStmnt (NonBlockAssign a) = genAssign " <= " a <> ";\n"
 genStmnt (StatCA a) = genContAssign a
-- 
cgit