From cabb2cec0bde620c49b1d7a36cd8226f579c1023 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Sun, 30 Dec 2018 19:44:40 +0100
Subject: [Fix #13, Fix #15] Fix type errors and add inst functions

---
 src/Test/VeriFuzz/Verilog/Helpers.hs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/Test/VeriFuzz/Verilog/Helpers.hs')

diff --git a/src/Test/VeriFuzz/Verilog/Helpers.hs b/src/Test/VeriFuzz/Verilog/Helpers.hs
index 4410532..6712d32 100644
--- a/src/Test/VeriFuzz/Verilog/Helpers.hs
+++ b/src/Test/VeriFuzz/Verilog/Helpers.hs
@@ -32,7 +32,7 @@ numExpr = ((PrimExpr . PrimNum) .) . Number
 
 -- | Create an empty module.
 emptyMod :: ModDecl
-emptyMod = ModDecl "" Nothing [] []
+emptyMod = ModDecl "" [] [] []
 
 -- | Set a module name for a module declaration.
 setModName :: Text -> ModDecl -> ModDecl
@@ -47,7 +47,7 @@ addDescription desc = getVerilogSrc %~ (:) desc
 
 testBench :: ModDecl
 testBench =
-  ModDecl "main" Nothing []
+  ModDecl "main" [] []
   [ regDecl "a"
   , regDecl "b"
   , wireDecl "c"
-- 
cgit