From de580a7d4b5f4def9f0b71c6cff33ccad45d678b Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Mon, 31 Dec 2018 19:13:25 +0100
Subject: Large refactor

---
 src/Test/VeriFuzz/Verilog/Helpers.hs | 18 +++++++-----------
 1 file changed, 7 insertions(+), 11 deletions(-)

(limited to 'src/Test/VeriFuzz/Verilog/Helpers.hs')

diff --git a/src/Test/VeriFuzz/Verilog/Helpers.hs b/src/Test/VeriFuzz/Verilog/Helpers.hs
index d3bc689..b04aa76 100644
--- a/src/Test/VeriFuzz/Verilog/Helpers.hs
+++ b/src/Test/VeriFuzz/Verilog/Helpers.hs
@@ -21,14 +21,10 @@ regDecl :: Identifier -> ModItem
 regDecl = Decl Nothing . Port (Reg False) 1
 
 wireDecl :: Identifier -> ModItem
-wireDecl = Decl Nothing . Port (PortNet Wire) 1
+wireDecl = Decl Nothing . Port Wire 1
 
-modConn :: Text -> ModConn
-modConn = ModConn . PrimExpr . PrimId . Identifier
-
--- | Create a number expression which will be stored in a primary expression.
-numExpr :: Int -> Int -> Expression
-numExpr = ((PrimExpr . PrimNum) .) . Number
+modConn :: Identifier -> ModConn
+modConn = ModConn . Id
 
 -- | Create an empty module.
 emptyMod :: ModDecl
@@ -57,10 +53,10 @@ testBench =
     , modConn "b"
     ]
   , Initial $ SeqBlock
-    [ BlockAssign . Assign (RegId "a") Nothing . PrimExpr . PrimNum $ Number 1 1
-    , BlockAssign . Assign (RegId "b") Nothing . PrimExpr . PrimNum $ Number 1 1
+    [ BlockAssign . Assign (RegId "a") Nothing $ Number 1 1
+    , BlockAssign . Assign (RegId "b") Nothing $ Number 1 1
     -- , TimeCtrl (Delay 1) . Just . SysTaskEnable $ Task "display"
-    --   [ ExprStr "%d & %d = %d"
+    --   [ Str "%d & %d = %d"
     --   , PrimExpr $ PrimId "a"
     --   , PrimExpr $ PrimId "b"
     --   , PrimExpr $ PrimId "c"
@@ -73,4 +69,4 @@ addTestBench :: VerilogSrc -> VerilogSrc
 addTestBench = addDescription $ Description testBench
 
 defaultPort :: Identifier -> Port
-defaultPort = Port (PortNet Wire) 1
+defaultPort = Port Wire 1
-- 
cgit