From 619965e928c10caf6fe430cf09c9bc09352ba071 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Mon, 31 Dec 2018 12:44:42 +0100
Subject: Add direction to Decl and add doctest

---
 src/Test/VeriFuzz/Verilog/AST.hs     |  6 ++++--
 src/Test/VeriFuzz/Verilog/CodeGen.hs |  5 +++--
 src/Test/VeriFuzz/Verilog/Helpers.hs |  4 ++--
 src/Test/VeriFuzz/Verilog/Mutate.hs  | 22 +++++++++++++++++-----
 4 files changed, 26 insertions(+), 11 deletions(-)

(limited to 'src/Test/VeriFuzz')

diff --git a/src/Test/VeriFuzz/Verilog/AST.hs b/src/Test/VeriFuzz/Verilog/AST.hs
index 33ccdb4..3ae595f 100644
--- a/src/Test/VeriFuzz/Verilog/AST.hs
+++ b/src/Test/VeriFuzz/Verilog/AST.hs
@@ -189,7 +189,9 @@ data ModItem = ModCA ContAssign
                        }
              | Initial Statement
              | Always Statement
-             | Decl Port
+             | Decl { declDir  :: Maybe PortDir
+                    , declPort :: Port
+                    }
              deriving (Show, Eq, Ord)
 
 -- | 'module' module_identifier [list_of_ports] ';' { module_item } 'end_module'
@@ -365,7 +367,7 @@ instance QC.Arbitrary ModItem where
                        , ModInst <$> QC.arbitrary <*> QC.arbitrary <*> QC.arbitrary
                        , Initial <$> QC.arbitrary
                        , Always <$> (EventCtrl <$> QC.arbitrary <*> QC.arbitrary)
-                       , Decl <$> QC.arbitrary
+                       , Decl <$> pure Nothing <*> QC.arbitrary
                        ]
 
 instance QC.Arbitrary ModDecl where
diff --git a/src/Test/VeriFuzz/Verilog/CodeGen.hs b/src/Test/VeriFuzz/Verilog/CodeGen.hs
index 0122b43..9902d32 100644
--- a/src/Test/VeriFuzz/Verilog/CodeGen.hs
+++ b/src/Test/VeriFuzz/Verilog/CodeGen.hs
@@ -47,7 +47,7 @@ genModuleDecl mod =
   where
     ports
       | noIn && noOut = ""
-      | otherwise = "(" <> (sep_ ", " $ genModPort <$> outIn) <> ")"
+      | otherwise = "(" <> (sep ", " $ genModPort <$> outIn) <> ")"
     modItems = fromList $ genModuleItem <$> mod ^. moduleItems
     noOut = null $ mod ^. modOutPorts
     noIn = null $ mod ^. modInPorts
@@ -80,7 +80,8 @@ genModuleItem (ModInst (Identifier id) (Identifier name) conn) =
   id <> " " <> name <> "(" <> sep ", " (genExpr . _modConn <$> conn) <> ")" <> ";\n"
 genModuleItem (Initial stat) = "initial " <> genStatement stat
 genModuleItem (Always stat) = "always " <> genStatement stat
-genModuleItem (Decl port) = genPort port <> ";\n"
+genModuleItem (Decl dir port) =
+  (fromMaybe "" $ ((<>" ") . genPortDir) <$> dir) <> genPort port <> ";\n"
 
 -- | Generate continuous assignment
 genContAssign :: ContAssign -> Text
diff --git a/src/Test/VeriFuzz/Verilog/Helpers.hs b/src/Test/VeriFuzz/Verilog/Helpers.hs
index 6712d32..d3bc689 100644
--- a/src/Test/VeriFuzz/Verilog/Helpers.hs
+++ b/src/Test/VeriFuzz/Verilog/Helpers.hs
@@ -18,10 +18,10 @@ import qualified Data.Text
 import           Test.VeriFuzz.Verilog.AST
 
 regDecl :: Identifier -> ModItem
-regDecl = Decl . Port (Reg False) 1
+regDecl = Decl Nothing . Port (Reg False) 1
 
 wireDecl :: Identifier -> ModItem
-wireDecl = Decl . Port (PortNet Wire) 1
+wireDecl = Decl Nothing . Port (PortNet Wire) 1
 
 modConn :: Text -> ModConn
 modConn = ModConn . PrimExpr . PrimId . Identifier
diff --git a/src/Test/VeriFuzz/Verilog/Mutate.hs b/src/Test/VeriFuzz/Verilog/Mutate.hs
index 4c032e7..847d890 100644
--- a/src/Test/VeriFuzz/Verilog/Mutate.hs
+++ b/src/Test/VeriFuzz/Verilog/Mutate.hs
@@ -20,6 +20,10 @@ import           Test.VeriFuzz.Internal.Shared
 import           Test.VeriFuzz.Verilog.AST
 import           Test.VeriFuzz.Verilog.CodeGen
 
+-- $setup
+-- >>> let mod = (ModDecl (Identifier "m") [Port (PortNet Wire) 5 (Identifier "y")] [Port (PortNet Wire) 5 "x"] [])
+-- >>> let main = (ModDecl "main" [] [] [])
+
 -- | Return if the 'Identifier' is in a 'ModDecl'.
 inPort :: Identifier -> ModDecl -> Bool
 inPort id mod = inInput
@@ -80,7 +84,7 @@ nestUpTo i src =
 -- it to the body of the second module. It first has to make all the inputs into
 -- @reg@.
 --
--- >>> SrcShow $ instantiateMod (ModDecl (Identifier "m") [Port (PortNet Wire) 5 (Identifier "y")] [Port (PortNet Wire) 5 "x"] []) (ModDecl "main" [] [] [])
+-- >>> SrcShow $ instantiateMod mod main
 -- module main;
 -- wire [4:0] y;
 -- reg [4:0] x;
@@ -90,11 +94,19 @@ instantiateMod :: ModDecl -> ModDecl -> ModDecl
 instantiateMod mod main =
   main & moduleItems %~ ((out ++ regIn)++)
   where
-    out = Decl <$> mod ^. modOutPorts
-    regIn = Decl <$> (mod ^. modInPorts & traverse . portType .~ Reg False)
+    out = Decl Nothing <$> mod ^. modOutPorts
+    regIn = Decl Nothing <$> (mod ^. modInPorts & traverse . portType .~ Reg False)
 
 -- | Initialise all the inputs and outputs to a module.
+--
+-- >>> SrcShow $ initMod mod
+-- module m(y, x);
+-- output wire [4:0] y;
+-- input wire [4:0] x;
+-- endmodule
+-- <BLANKLINE>
 initMod :: ModDecl -> ModDecl
-initMod mod = mod & moduleItems %~ (inOut++)
+initMod mod = mod & moduleItems %~ ((out ++ inp)++)
   where
-    inOut = Decl <$> (mod ^. modOutPorts) ++ (mod ^. modInPorts)
+    out = Decl (Just PortOut) <$> (mod ^. modOutPorts)
+    inp = Decl (Just PortIn) <$> (mod ^. modInPorts)
-- 
cgit