From 922e0e3cfa9b8b77f7099c2b85c2a974aa6ff948 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Sat, 22 Dec 2018 15:21:38 +0000
Subject: Format ASTGen

---
 src/Test/VeriFuzz/Graph/ASTGen.hs | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

(limited to 'src/Test/VeriFuzz')

diff --git a/src/Test/VeriFuzz/Graph/ASTGen.hs b/src/Test/VeriFuzz/Graph/ASTGen.hs
index 97b6c1c..d3e6ea5 100644
--- a/src/Test/VeriFuzz/Graph/ASTGen.hs
+++ b/src/Test/VeriFuzz/Graph/ASTGen.hs
@@ -62,20 +62,17 @@ genContAssignAST c (n, g) = ContAssign name <$> genAssignExpr g nodes
     name = frNode n
 
 genAssignAST :: Circuit -> [ContAssign]
-genAssignAST c =
-  catMaybes $ genContAssignAST c <$> nodes
+genAssignAST c = catMaybes $ genContAssignAST c <$> nodes
   where
     gr = getCircuit c
     nodes = G.labNodes gr
 
 genModuleDeclAST :: Circuit -> ModuleDecl
-genModuleDeclAST c =
-  ModuleDecl id ports items
+genModuleDeclAST c = ModuleDecl id ports items
   where
     id = Identifier "gen_module"
     ports = genPortsAST c
     items = Assign <$> genAssignAST c
 
 generateAST :: Circuit -> SourceText
-generateAST c =
-  SourceText [Description $ genModuleDeclAST c]
+generateAST c = SourceText [Description $ genModuleDeclAST c]
-- 
cgit