From 88ffe371e6a2ac5892b5249698f6f8ab1c323ee2 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Fri, 30 Nov 2018 20:50:40 +0000
Subject: Add lens library and extend types for AST

---
 src/Test/VeriFuzz/VerilogAST.hs | 70 ++++++++++++++++++++++++++++++++++++++---
 1 file changed, 65 insertions(+), 5 deletions(-)

(limited to 'src/Test')

diff --git a/src/Test/VeriFuzz/VerilogAST.hs b/src/Test/VeriFuzz/VerilogAST.hs
index 897855b..e4d19ec 100644
--- a/src/Test/VeriFuzz/VerilogAST.hs
+++ b/src/Test/VeriFuzz/VerilogAST.hs
@@ -1,13 +1,73 @@
+{-# LANGUAGE TemplateHaskell #-}
+
 module Test.VeriFuzz.VerilogAST where
 
-data ModuleItem = 
+import           Control.Lens
+import           Data.Text    (Text)
+import qualified Data.Text    as T
 
--- | 'module' module_identifier [list_of_ports] ';' { module_item } 'end_module'
-data ModuleDecl = ModuleDecl { moduleId   :: Text
-                             , ports      :: [Port]
-                             , moduleItem :: ModuleItem
+type NetLVal = Text
+
+type Identifier = Text
+
+data Number = Number { _numSize :: Int
+                     , _numVal  :: Int
+                     } deriving (Show)
+
+data BinaryOperator = BinAnd
+                    | BinOr
+                    | BinXor
+                    deriving (Show)
+
+data UnaryOperator = UnNot
+                   | UnMinus
+                   deriving (Show)
+
+data Primary = PrimNum Number
+             | PrimId Identifier
+             deriving (Show)
+
+data Expression = PrimExpr Primary
+                | UnPrimExpr { _exprUnOp :: UnaryOperator
+                             , _exprPrim :: Primary
                              }
+                | OpExpr { _exprLhs   :: Expression
+                         , _exprBinOp :: BinaryOperator
+                         , _exprRhs   :: Expression
+                         }
+                | CondExpr { _exprCond  :: Expression
+                           , _exprTrue  :: Expression
+                           , _exprFalse :: Expression
+                           }
+                deriving (Show)
+
+data ContAssign = ContAssign { _contAssignNetLVal :: NetLVal
+                             , _contAssignExpr    :: Expression
+                             } deriving (Show)
+
+data PortDir = Input
+             | Output
+             | InOut
+             deriving (Show)
+
+data Port = Port { _portName :: Identifier
+                 , _portDir  :: PortDir
+                 } deriving (Show)
+
+type ModuleItem = Text
+
+-- | 'module' module_identifier [list_of_ports] ';' { module_item } 'end_module'
+data ModuleDecl = ModuleDecl { _moduleId   :: Identifier
+                             , _modPorts   :: [Port]
+                             , _moduleItem :: ModuleItem
+                             } deriving (Show)
 
 type Description = ModuleDecl
 
 type SourceText = [Description]
+
+makeLenses ''Number
+makeLenses ''Expression
+makeLenses ''ContAssign
+makeLenses ''Port
+makeLenses ''ModuleDecl
-- 
cgit