From 8e4fab352bad77b91b248c1f50e1b0554793b689 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Sat, 29 Dec 2018 23:41:26 +0100
Subject: Fix verilog output for output port

---
 src/Test/VeriFuzz/Verilog/CodeGen.hs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/Test')

diff --git a/src/Test/VeriFuzz/Verilog/CodeGen.hs b/src/Test/VeriFuzz/Verilog/CodeGen.hs
index e1114d2..7861294 100644
--- a/src/Test/VeriFuzz/Verilog/CodeGen.hs
+++ b/src/Test/VeriFuzz/Verilog/CodeGen.hs
@@ -47,7 +47,7 @@ genModuleDecl mod =
   where
     ports
       | noIn && noOut = ""
-      | otherwise = "(" <> out <> (sep ", " $ genModPort <$> mod ^. modInPorts) <> ")"
+      | otherwise = "(" <> out <> (sep_ ", " $ genModPort <$> mod ^. modInPorts) <> ")"
     modItems = fromList $ genModuleItem <$> mod ^. moduleItems
     noOut = isNothing $ mod ^. modOutPort
     noIn = null $ mod ^. modInPorts
-- 
cgit