From 9f2bb8aff3198d36ac847dde67e4e630cd8b889f Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Sun, 30 Dec 2018 19:44:00 +0100
Subject: Change modPort type from Maybe to List

---
 src/Test/VeriFuzz/Verilog/AST.hs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/Test')

diff --git a/src/Test/VeriFuzz/Verilog/AST.hs b/src/Test/VeriFuzz/Verilog/AST.hs
index 65be816..33ccdb4 100644
--- a/src/Test/VeriFuzz/Verilog/AST.hs
+++ b/src/Test/VeriFuzz/Verilog/AST.hs
@@ -194,7 +194,7 @@ data ModItem = ModCA ContAssign
 
 -- | 'module' module_identifier [list_of_ports] ';' { module_item } 'end_module'
 data ModDecl = ModDecl { _moduleId    :: Identifier
-                       , _modOutPort  :: Maybe Port
+                       , _modOutPorts :: [Port]
                        , _modInPorts  :: [Port]
                        , _moduleItems :: [ModItem]
                        } deriving (Show, Eq, Ord)
-- 
cgit