From 31325e890e8a7807ec5a3d996c3789baad0e8dc4 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Wed, 3 Apr 2019 19:53:56 +0100
Subject: Generate Verilog instead of ModDecl

---
 src/VeriFuzz.hs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/VeriFuzz.hs')

diff --git a/src/VeriFuzz.hs b/src/VeriFuzz.hs
index e008d62..b6b134b 100644
--- a/src/VeriFuzz.hs
+++ b/src/VeriFuzz.hs
@@ -113,10 +113,10 @@ checkEquivalence src dir = shellyFailDir $ do
 
 -- | Run a fuzz run and check if all of the simulators passed by checking if the
 -- generated Verilog files are equivalent.
-runEquivalence :: Gen ModDecl -> Text -> Int -> IO ()
+runEquivalence :: Gen Verilog -> Text -> Int -> IO ()
 runEquivalence gm t i = do
     m <- Hog.sample gm
-    let srcInfo = makeSrcInfo m
+    let srcInfo = SourceInfo "top" m
     rand <- generateByteString 20
     shellyFailDir $ do
         mkdir_p (fromText "output" </> fromText n)
-- 
cgit