From 93cbc45b1ed7887af8f2c3d054f5da6b08ce9211 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Grave Date: Wed, 6 Mar 2019 16:18:48 +0000 Subject: Fix positive arbitrary generation --- src/VeriFuzz/AST.hs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/VeriFuzz/AST.hs') diff --git a/src/VeriFuzz/AST.hs b/src/VeriFuzz/AST.hs index a2ebb32..d37b053 100644 --- a/src/VeriFuzz/AST.hs +++ b/src/VeriFuzz/AST.hs @@ -131,7 +131,7 @@ import Data.Traversable (sequenceA) import qualified Test.QuickCheck as QC positiveArb :: (QC.Arbitrary a, Ord a, Num a) => QC.Gen a -positiveArb = QC.suchThat QC.arbitrary (> 0) +positiveArb = abs <$> QC.suchThat QC.arbitrary (/= 0) -- | Identifier in Verilog. This is just a string of characters that can either -- be lowercase and uppercase for now. This might change in the future though, -- cgit