From c0c799ab3f79c370e4c33b8f824489ce8b1c96ec Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Tue, 2 Apr 2019 18:16:21 +0100 Subject: Rename to Verilog --- src/VeriFuzz/ASTGen.hs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/VeriFuzz/ASTGen.hs') diff --git a/src/VeriFuzz/ASTGen.hs b/src/VeriFuzz/ASTGen.hs index 7c295e1..9360a88 100644 --- a/src/VeriFuzz/ASTGen.hs +++ b/src/VeriFuzz/ASTGen.hs @@ -75,5 +75,5 @@ genModuleDeclAST c = ModDecl i output ports $ combineAssigns yPort a a = genAssignAST c yPort = Port Wire False 90 "y" -generateAST :: Circuit -> VerilogSrc -generateAST c = VerilogSrc [Description $ genModuleDeclAST c] +generateAST :: Circuit -> Verilog +generateAST c = Verilog [Description $ genModuleDeclAST c] -- cgit