From fd4b0b5152f94cd406f2e5de86ce7ed0a4d2cbd0 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Tue, 2 Apr 2019 19:47:32 +0100
Subject: Large refactor with passing tests

---
 src/VeriFuzz/Circuit/Base.hs | 42 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 src/VeriFuzz/Circuit/Base.hs

(limited to 'src/VeriFuzz/Circuit/Base.hs')

diff --git a/src/VeriFuzz/Circuit/Base.hs b/src/VeriFuzz/Circuit/Base.hs
new file mode 100644
index 0000000..6b9f725
--- /dev/null
+++ b/src/VeriFuzz/Circuit/Base.hs
@@ -0,0 +1,42 @@
+{-|
+Module      : VeriFuzz.Circuit.Base
+Description : Base types for the circuit module.
+Copyright   : (c) 2019, Yann Herklotz Grave
+License     : GPL-3
+Maintainer  : ymherklotz [at] gmail [dot] com
+Stability   : experimental
+Portability : POSIX
+
+Base types for the circuit module.
+-}
+
+module VeriFuzz.Circuit.Base
+    ( Gate(..)
+    , Circuit(..)
+    , CNode(..)
+    , CEdge(..)
+    )
+where
+
+import           Data.Graph.Inductive (Gr, LEdge, LNode)
+import           System.Random
+
+-- | The types for all the gates.
+data Gate = And
+          | Or
+          | Xor
+          deriving (Show, Eq, Enum, Bounded, Ord)
+
+-- | Newtype for the Circuit which implements a Graph from fgl.
+newtype Circuit = Circuit { getCircuit :: Gr Gate () }
+
+newtype CNode = CNode { getCNode :: LNode Gate }
+
+newtype CEdge = CEdge { getCEdge :: LEdge () }
+
+instance Random Gate where
+  randomR (a, b) g =
+    case randomR (fromEnum a, fromEnum b) g of
+      (x, g') -> (toEnum x, g')
+
+  random = randomR (minBound, maxBound)
-- 
cgit