From cccb665ebac6e916c4f961eacbe11a9af7d7ceb3 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Thu, 29 Aug 2019 15:44:33 +1000
Subject: Change name from VeriFuzz to VeriSmith

---
 src/VeriFuzz/Circuit/Gen.hs | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

(limited to 'src/VeriFuzz/Circuit/Gen.hs')

diff --git a/src/VeriFuzz/Circuit/Gen.hs b/src/VeriFuzz/Circuit/Gen.hs
index eb7cb97..1c4dd37 100644
--- a/src/VeriFuzz/Circuit/Gen.hs
+++ b/src/VeriFuzz/Circuit/Gen.hs
@@ -10,18 +10,18 @@ Portability : POSIX
 Generate verilog from circuit.
 -}
 
-module VeriFuzz.Circuit.Gen
+module VeriSmith.Circuit.Gen
     ( generateAST
     )
 where
 
-import           Data.Graph.Inductive      (LNode, Node)
-import qualified Data.Graph.Inductive      as G
-import           Data.Maybe                (catMaybes)
-import           VeriFuzz.Circuit.Base
-import           VeriFuzz.Circuit.Internal
-import           VeriFuzz.Verilog.AST
-import           VeriFuzz.Verilog.Mutate
+import           Data.Graph.Inductive       (LNode, Node)
+import qualified Data.Graph.Inductive       as G
+import           Data.Maybe                 (catMaybes)
+import           VeriSmith.Circuit.Base
+import           VeriSmith.Circuit.Internal
+import           VeriSmith.Verilog.AST
+import           VeriSmith.Verilog.Mutate
 
 -- | Converts a 'CNode' to an 'Identifier'.
 frNode :: Node -> Identifier
-- 
cgit 


From a2b01b92612a098673ff03890e6e8aef4ceb28ea Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Wed, 4 Sep 2019 20:15:51 +1000
Subject: Renaming to VeriSmith

---
 src/VeriFuzz/Circuit/Gen.hs | 79 ---------------------------------------------
 1 file changed, 79 deletions(-)
 delete mode 100644 src/VeriFuzz/Circuit/Gen.hs

(limited to 'src/VeriFuzz/Circuit/Gen.hs')

diff --git a/src/VeriFuzz/Circuit/Gen.hs b/src/VeriFuzz/Circuit/Gen.hs
deleted file mode 100644
index 1c4dd37..0000000
--- a/src/VeriFuzz/Circuit/Gen.hs
+++ /dev/null
@@ -1,79 +0,0 @@
-{-|
-Module      : Verilog.Circuit.Gen
-Description : Generate verilog from circuit.
-Copyright   : (c) 2019, Yann Herklotz Grave
-License     : GPL-3
-Maintainer  : yann [at] yannherklotz [dot] com
-Stability   : experimental
-Portability : POSIX
-
-Generate verilog from circuit.
--}
-
-module VeriSmith.Circuit.Gen
-    ( generateAST
-    )
-where
-
-import           Data.Graph.Inductive       (LNode, Node)
-import qualified Data.Graph.Inductive       as G
-import           Data.Maybe                 (catMaybes)
-import           VeriSmith.Circuit.Base
-import           VeriSmith.Circuit.Internal
-import           VeriSmith.Verilog.AST
-import           VeriSmith.Verilog.Mutate
-
--- | Converts a 'CNode' to an 'Identifier'.
-frNode :: Node -> Identifier
-frNode = Identifier . fromNode
-
--- | Converts a 'Gate' to a 'BinaryOperator', which should be a bijective
--- mapping.
-fromGate :: Gate -> BinaryOperator
-fromGate And = BinAnd
-fromGate Or  = BinOr
-fromGate Xor = BinXor
-
-inputsC :: Circuit -> [Node]
-inputsC c = inputs (getCircuit c)
-
-genPortsAST :: (Circuit -> [Node]) -> Circuit -> [Port]
-genPortsAST f c = port . frNode <$> f c where port = Port Wire False 4
-
--- | Generates the nested expression AST, so that it can then generate the
--- assignment expressions.
-genAssignExpr :: Gate -> [Node] -> Maybe Expr
-genAssignExpr _ []       = Nothing
-genAssignExpr _ [n     ] = Just . Id $ frNode n
-genAssignExpr g (n : ns) = BinOp wire oper <$> genAssignExpr g ns
-  where
-    wire = Id $ frNode n
-    oper = fromGate g
-
--- | Generate the continuous assignment AST for a particular node. If it does
--- not have any nodes that link to it then return 'Nothing', as that means that
--- the assignment will just be empty.
-genContAssignAST :: Circuit -> LNode Gate -> Maybe ModItem
-genContAssignAST c (n, g) = ModCA . ContAssign name <$> genAssignExpr g nodes
-  where
-    gr    = getCircuit c
-    nodes = G.pre gr n
-    name  = frNode n
-
-genAssignAST :: Circuit -> [ModItem]
-genAssignAST c = catMaybes $ genContAssignAST c <$> nodes
-  where
-    gr    = getCircuit c
-    nodes = G.labNodes gr
-
-genModuleDeclAST :: Circuit -> ModDecl
-genModuleDeclAST c = ModDecl i output ports (combineAssigns yPort a) []
-  where
-    i      = Identifier "gen_module"
-    ports  = genPortsAST inputsC c
-    output = []
-    a      = genAssignAST c
-    yPort  = Port Wire False 90 "y"
-
-generateAST :: Circuit -> Verilog
-generateAST c = Verilog [genModuleDeclAST c]
-- 
cgit