From cccb665ebac6e916c4f961eacbe11a9af7d7ceb3 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Thu, 29 Aug 2019 15:44:33 +1000
Subject: Change name from VeriFuzz to VeriSmith

---
 src/VeriFuzz/Circuit/Base.hs     |  4 ++--
 src/VeriFuzz/Circuit/Gen.hs      | 16 ++++++++--------
 src/VeriFuzz/Circuit/Internal.hs |  4 ++--
 src/VeriFuzz/Circuit/Random.hs   |  6 +++---
 4 files changed, 15 insertions(+), 15 deletions(-)

(limited to 'src/VeriFuzz/Circuit')

diff --git a/src/VeriFuzz/Circuit/Base.hs b/src/VeriFuzz/Circuit/Base.hs
index 0bcdf39..ddcaf65 100644
--- a/src/VeriFuzz/Circuit/Base.hs
+++ b/src/VeriFuzz/Circuit/Base.hs
@@ -1,5 +1,5 @@
 {-|
-Module      : VeriFuzz.Circuit.Base
+Module      : VeriSmith.Circuit.Base
 Description : Base types for the circuit module.
 Copyright   : (c) 2019, Yann Herklotz Grave
 License     : GPL-3
@@ -10,7 +10,7 @@ Portability : POSIX
 Base types for the circuit module.
 -}
 
-module VeriFuzz.Circuit.Base
+module VeriSmith.Circuit.Base
     ( Gate(..)
     , Circuit(..)
     , CNode(..)
diff --git a/src/VeriFuzz/Circuit/Gen.hs b/src/VeriFuzz/Circuit/Gen.hs
index eb7cb97..1c4dd37 100644
--- a/src/VeriFuzz/Circuit/Gen.hs
+++ b/src/VeriFuzz/Circuit/Gen.hs
@@ -10,18 +10,18 @@ Portability : POSIX
 Generate verilog from circuit.
 -}
 
-module VeriFuzz.Circuit.Gen
+module VeriSmith.Circuit.Gen
     ( generateAST
     )
 where
 
-import           Data.Graph.Inductive      (LNode, Node)
-import qualified Data.Graph.Inductive      as G
-import           Data.Maybe                (catMaybes)
-import           VeriFuzz.Circuit.Base
-import           VeriFuzz.Circuit.Internal
-import           VeriFuzz.Verilog.AST
-import           VeriFuzz.Verilog.Mutate
+import           Data.Graph.Inductive       (LNode, Node)
+import qualified Data.Graph.Inductive       as G
+import           Data.Maybe                 (catMaybes)
+import           VeriSmith.Circuit.Base
+import           VeriSmith.Circuit.Internal
+import           VeriSmith.Verilog.AST
+import           VeriSmith.Verilog.Mutate
 
 -- | Converts a 'CNode' to an 'Identifier'.
 frNode :: Node -> Identifier
diff --git a/src/VeriFuzz/Circuit/Internal.hs b/src/VeriFuzz/Circuit/Internal.hs
index 17e1586..b746738 100644
--- a/src/VeriFuzz/Circuit/Internal.hs
+++ b/src/VeriFuzz/Circuit/Internal.hs
@@ -1,5 +1,5 @@
 {-|
-Module      : VeriFuzz.Circuit.Internal
+Module      : VeriSmith.Circuit.Internal
 Description : Internal helpers for generation.
 Copyright   : (c) 2018-2019, Yann Herklotz
 License     : BSD-3
@@ -10,7 +10,7 @@ Portability : POSIX
 Internal helpers for generation.
 -}
 
-module VeriFuzz.Circuit.Internal
+module VeriSmith.Circuit.Internal
     ( fromNode
     , filterGr
     , only
diff --git a/src/VeriFuzz/Circuit/Random.hs b/src/VeriFuzz/Circuit/Random.hs
index fdb5253..ca8cc26 100644
--- a/src/VeriFuzz/Circuit/Random.hs
+++ b/src/VeriFuzz/Circuit/Random.hs
@@ -1,5 +1,5 @@
 {-|
-Module      : VeriFuzz.Circuit.Random
+Module      : VeriSmith.Circuit.Random
 Description : Random generation for DAG
 Copyright   : (c) 2018-2019, Yann Herklotz
 License     : BSD-3
@@ -10,7 +10,7 @@ Portability : POSIX
 Define the random generation for the directed acyclic graph.
 -}
 
-module VeriFuzz.Circuit.Random
+module VeriSmith.Circuit.Random
     ( rDups
     , rDupsCirc
     , randomDAG
@@ -25,7 +25,7 @@ import           Data.List                         (nub)
 import           Hedgehog                          (Gen)
 import qualified Hedgehog.Gen                      as Hog
 import qualified Hedgehog.Range                    as Hog
-import           VeriFuzz.Circuit.Base
+import           VeriSmith.Circuit.Base
 
 dupFolder :: (Eq a, Eq b) => Context a b -> [Context a b] -> [Context a b]
 dupFolder cont ns = unique cont : ns
-- 
cgit