From 5025a43948a682bc40d5c91606ec97cd8d6c3897 Mon Sep 17 00:00:00 2001
From: Yann Herklotz Grave <git@yannherklotzgrave.com>
Date: Sat, 16 Feb 2019 20:19:00 +0000
Subject: Change Port type, adding signed info

---
 src/VeriFuzz/CodeGen.hs | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

(limited to 'src/VeriFuzz/CodeGen.hs')

diff --git a/src/VeriFuzz/CodeGen.hs b/src/VeriFuzz/CodeGen.hs
index f35eff7..3e36cf5 100644
--- a/src/VeriFuzz/CodeGen.hs
+++ b/src/VeriFuzz/CodeGen.hs
@@ -68,12 +68,17 @@ genModPort port = port ^. portName . getIdentifier
 
 -- | Generate the 'Port' description.
 genPort :: Port -> Text
-genPort port = t <> size <> name
+genPort port = t <> sign <> size <> name
  where
-  t = (<> " ") . genPortType $ port ^. portType
+  t = flip mappend " " . genPortType $ port ^. portType
   size | port ^. portSize > 1 = "[" <> showT (port ^. portSize - 1) <> ":0] "
        | otherwise            = ""
   name = port ^. portName . getIdentifier
+  sign = genSigned $ port ^. portSigned
+
+genSigned :: Bool -> Text
+genSigned True = "signed "
+genSigned _    = ""
 
 -- | Convert the 'PortDir' type to 'Text'.
 genPortDir :: PortDir -> Text
@@ -188,8 +193,7 @@ genConstExpr (ConstExpr num) = showT num
 
 genPortType :: PortType -> Text
 genPortType Wire = "wire"
-genPortType (Reg signed) | signed    = "reg signed"
-                         | otherwise = "reg"
+genPortType Reg  = "reg"
 
 genAssign :: Text -> Assign -> Text
 genAssign op (Assign r d e) = genLVal r <> op <> maybe "" genDelay d <> genExpr e
-- 
cgit