From 928a54419aeac611555b3c15493db00010cbb46e Mon Sep 17 00:00:00 2001
From: Yann Herklotz Grave <git@yannherklotzgrave.com>
Date: Sun, 17 Feb 2019 12:37:46 +0000
Subject: Indent by 4

---
 src/VeriFuzz/Gen.hs | 48 ++++++++++++++++++++++++------------------------
 1 file changed, 24 insertions(+), 24 deletions(-)

(limited to 'src/VeriFuzz/Gen.hs')

diff --git a/src/VeriFuzz/Gen.hs b/src/VeriFuzz/Gen.hs
index 724b00d..3413ee6 100644
--- a/src/VeriFuzz/Gen.hs
+++ b/src/VeriFuzz/Gen.hs
@@ -28,45 +28,45 @@ toId = Identifier . ("w" <>) . T.pack . show
 
 toPort :: Identifier -> Gen Port
 toPort ident = do
-  i <- abs <$> QC.arbitrary
-  return $ wire i ident
+    i <- abs <$> QC.arbitrary
+    return $ wire i ident
 
 sumSize :: [Port] -> Int
 sumSize ports = sum $ ports ^.. traverse . portSize
 
 random :: [Identifier] -> (Expr -> ContAssign) -> Gen ModItem
 random ctx fun = do
-  expr <- QC.sized (exprWithContext ctx)
-  return . ModCA $ fun expr
+    expr <- QC.sized (exprWithContext ctx)
+    return . ModCA $ fun expr
 
 randomAssigns :: [Identifier] -> [Gen ModItem]
 randomAssigns ids = random ids . ContAssign <$> ids
 
 randomOrdAssigns :: [Identifier] -> [Identifier] -> [Gen ModItem]
 randomOrdAssigns inp ids = snd $ foldr gen (inp, []) ids
-  where gen cid (i, o) = (cid : i, random i (ContAssign cid) : o)
+    where gen cid (i, o) = (cid : i, random i (ContAssign cid) : o)
 
 randomMod :: Int -> Int -> Gen ModDecl
 randomMod inps total = do
-  x     <- sequence $ randomOrdAssigns start end
-  ident <- sequence $ toPort <$> ids
-  let inputs_ = take inps ident
-  let other   = drop inps ident
-  let y = ModCA . ContAssign "y" . fold $ Id <$> drop inps ids
-  let yport   = [wire (sumSize other) "y"]
-  return . initMod . declareMod other . ModDecl "test_module" yport inputs_ $ x ++ [y]
- where
-  ids   = toId <$> [1 .. total]
-  end   = drop inps ids
-  start = take inps ids
+    x     <- sequence $ randomOrdAssigns start end
+    ident <- sequence $ toPort <$> ids
+    let inputs_ = take inps ident
+    let other   = drop inps ident
+    let y = ModCA . ContAssign "y" . fold $ Id <$> drop inps ids
+    let yport   = [wire (sumSize other) "y"]
+    return . initMod . declareMod other . ModDecl "test_module" yport inputs_ $ x ++ [y]
+  where
+    ids   = toId <$> [1 .. total]
+    end   = drop inps ids
+    start = take inps ids
 
 fromGraph :: Gen ModDecl
 fromGraph = do
-  gr <- rDupsCirc <$> QC.resize 100 randomCircuit
-  return
-    $   initMod
-    .   head
-    $   nestUpTo 5 (generateAST gr)
-    ^.. getVerilogSrc
-    .   traverse
-    .   getDescription
+    gr <- rDupsCirc <$> QC.resize 100 randomCircuit
+    return
+        $   initMod
+        .   head
+        $   nestUpTo 5 (generateAST gr)
+        ^.. getVerilogSrc
+        .   traverse
+        .   getDescription
-- 
cgit