From c0c799ab3f79c370e4c33b8f824489ce8b1c96ec Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Tue, 2 Apr 2019 18:16:21 +0100 Subject: Rename to Verilog --- src/VeriFuzz/Gen.hs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/VeriFuzz/Gen.hs') diff --git a/src/VeriFuzz/Gen.hs b/src/VeriFuzz/Gen.hs index b9545a8..6bc01c9 100644 --- a/src/VeriFuzz/Gen.hs +++ b/src/VeriFuzz/Gen.hs @@ -75,7 +75,7 @@ fromGraph = do $ initMod . head $ nestUpTo 5 (generateAST gr) - ^.. getVerilogSrc + ^.. getVerilog . traverse . getDescription @@ -206,8 +206,8 @@ moduleDef top = do -- | Procedural generation method for random Verilog. Uses internal 'Reader' and -- 'State' to keep track of the current Verilog code structure. -procedural :: Config -> Gen VerilogSrc -procedural config = VerilogSrc . (: []) . Description <$> Hog.resize +procedural :: Config -> Gen Verilog +procedural config = Verilog . (: []) . Description <$> Hog.resize num (runReaderT (evalStateT (moduleDef True) context) config) where -- cgit