From 4ba440d842e9a0502b429fbc04e2be41c8037a4c Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Sat, 19 Jan 2019 19:20:33 +0000
Subject: Add brittany formatting instead of stylish-haskell

---
 src/VeriFuzz/Graph/ASTGen.hs | 58 +++++++++++++++++++++-----------------------
 1 file changed, 28 insertions(+), 30 deletions(-)

(limited to 'src/VeriFuzz/Graph/ASTGen.hs')

diff --git a/src/VeriFuzz/Graph/ASTGen.hs b/src/VeriFuzz/Graph/ASTGen.hs
index f7bd058..0403f51 100644
--- a/src/VeriFuzz/Graph/ASTGen.hs
+++ b/src/VeriFuzz/Graph/ASTGen.hs
@@ -12,10 +12,12 @@ Generates the AST from the graph directly.
 
 module VeriFuzz.Graph.ASTGen where
 
-import           Data.Foldable            (fold)
-import           Data.Graph.Inductive     (LNode, Node)
-import qualified Data.Graph.Inductive     as G
-import           Data.Maybe               (catMaybes)
+import           Data.Foldable                  ( fold )
+import           Data.Graph.Inductive           ( LNode
+                                                , Node
+                                                )
+import qualified Data.Graph.Inductive          as G
+import           Data.Maybe                     ( catMaybes )
 import           VeriFuzz.Circuit
 import           VeriFuzz.Internal.Gen
 import           VeriFuzz.Verilog.AST
@@ -33,52 +35,48 @@ fromGate Or  = BinOr
 fromGate Xor = BinXor
 
 inputsC :: Circuit -> [Node]
-inputsC c =
-  inputs (getCircuit c)
+inputsC c = inputs (getCircuit c)
 
 outputsC :: Circuit -> [Node]
-outputsC c =
-  outputs (getCircuit c)
+outputsC c = outputs (getCircuit c)
 
 genPortsAST :: (Circuit -> [Node]) -> Circuit -> [Port]
-genPortsAST f c =
-  port . frNode <$> f c
-  where
-    port = Port Wire 4
+genPortsAST f c = port . frNode <$> f c where port = Port Wire 4
 
 -- | Generates the nested expression AST, so that it can then generate the
 -- assignment expressions.
 genAssignExpr :: Gate -> [Node] -> Maybe Expr
-genAssignExpr _ [] = Nothing
-genAssignExpr _ [n] = Just . Id $ frNode n
-genAssignExpr g (n:ns) = BinOp wire op <$> genAssignExpr g ns
-  where
-    wire = Id $ frNode n
-    op = fromGate g
+genAssignExpr _ []       = Nothing
+genAssignExpr _ [n     ] = Just . Id $ frNode n
+genAssignExpr g (n : ns) = BinOp wire op <$> genAssignExpr g ns
+ where
+  wire = Id $ frNode n
+  op   = fromGate g
 
 -- | Generate the continuous assignment AST for a particular node. If it does
 -- not have any nodes that link to it then return 'Nothing', as that means that
 -- the assignment will just be empty.
 genContAssignAST :: Circuit -> LNode Gate -> Maybe ModItem
 genContAssignAST c (n, g) = ModCA . ContAssign name <$> genAssignExpr g nodes
-  where
-    gr = getCircuit c
-    nodes = G.pre gr n
-    name = frNode n
+ where
+  gr    = getCircuit c
+  nodes = G.pre gr n
+  name  = frNode n
 
 genAssignAST :: Circuit -> [ModItem]
 genAssignAST c = catMaybes $ genContAssignAST c <$> nodes
-  where
-    gr = getCircuit c
-    nodes = G.labNodes gr
+ where
+  gr    = getCircuit c
+  nodes = G.labNodes gr
 
 genModuleDeclAST :: Circuit -> ModDecl
 genModuleDeclAST c = ModDecl i output ports items
-  where
-    i = Identifier "gen_module"
-    ports = genPortsAST inputsC c
-    output = [Port Wire 90 "y"]
-    items = genAssignAST c ++ [ModCA . ContAssign "y" . fold $ portToExpr <$> ports]
+ where
+  i      = Identifier "gen_module"
+  ports  = genPortsAST inputsC c
+  output = [Port Wire 90 "y"]
+  items =
+    genAssignAST c ++ [ModCA . ContAssign "y" . fold $ portToExpr <$> ports]
 
 generateAST :: Circuit -> VerilogSrc
 generateAST c = VerilogSrc [Description $ genModuleDeclAST c]
-- 
cgit