From 1067284cc1f6ca8ba646545c5b8d0a79cc2e41ad Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Fri, 1 Feb 2019 19:39:52 +0000 Subject: More restructuring --- src/VeriFuzz/Icarus.hs | 63 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 src/VeriFuzz/Icarus.hs (limited to 'src/VeriFuzz/Icarus.hs') diff --git a/src/VeriFuzz/Icarus.hs b/src/VeriFuzz/Icarus.hs new file mode 100644 index 0000000..527322a --- /dev/null +++ b/src/VeriFuzz/Icarus.hs @@ -0,0 +1,63 @@ +{-| +Module : VeriFuzz.Simulator.Icarus +Description : Icarus verilog module. +Copyright : (c) 2018-2019, Yann Herklotz Grave +License : BSD-3 +Maintainer : ymherklotz [at] gmail [dot] com +Stability : experimental +Portability : POSIX + +Icarus verilog module. +-} + +module VeriFuzz.Simulator.Icarus where + +import Control.Lens +import Data.ByteString (ByteString) +import qualified Data.ByteString as B +import Data.Foldable (fold) +import Data.Hashable +import Data.List (transpose) +import Prelude hiding (FilePath) +import Shelly +import VeriFuzz.Simulator.General +import VeriFuzz.Verilog + +data Icarus = Icarus { icarusPath :: FilePath + , vvpPath :: FilePath + } + +instance Simulator Icarus where + toText _ = "iverilog" + +instance Simulate Icarus where + runSim = runSimIcarus + +defaultIcarus :: Icarus +defaultIcarus = Icarus "iverilog" "vvp" + +addDisplay :: [Stmnt] -> [Stmnt] +addDisplay s = concat $ transpose + [s, replicate l $ TimeCtrl 1 Nothing, replicate l . SysTaskEnable $ Task "display" ["%h", Id "y"]] + where l = length s + +assignFunc :: [Port] -> ByteString -> Stmnt +assignFunc inp bs = NonBlockAssign . Assign conc Nothing . Number (B.length bs * 4) $ bsToI bs + where conc = RegConcat (portToExpr <$> inp) + +runSimIcarus :: Icarus -> ModDecl -> [ByteString] -> Sh Int +runSimIcarus sim m bss = do + let tb = ModDecl + "main" + [] + [] + [ Initial + $ fold (addDisplay $ assignFunc (m ^. modInPorts) <$> bss) + <> (SysTaskEnable $ Task "finish" []) + ] + let newtb = instantiateMod m tb + let modWithTb = VerilogSrc $ Description <$> [newtb, m] + writefile "main.v" $ genSource modWithTb + echoP "Run icarus" + noPrint $ run_ (icarusPath sim) ["-o", "main", "main.v"] + hash <$> run (vvpPath sim) ["main"] -- cgit