From c0c799ab3f79c370e4c33b8f824489ce8b1c96ec Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Tue, 2 Apr 2019 18:16:21 +0100
Subject: Rename to Verilog

---
 src/VeriFuzz/Icarus.hs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/VeriFuzz/Icarus.hs')

diff --git a/src/VeriFuzz/Icarus.hs b/src/VeriFuzz/Icarus.hs
index 32c4013..47159b3 100644
--- a/src/VeriFuzz/Icarus.hs
+++ b/src/VeriFuzz/Icarus.hs
@@ -89,7 +89,7 @@ runSimIcarus sim rinfo bss = do
               <> (SysTaskEnable $ Task "finish" [])
             ]
     let newtb     = instantiateMod m tb
-    let modWithTb = VerilogSrc $ Description <$> [newtb, m]
+    let modWithTb = Verilog $ Description <$> [newtb, m]
     writefile "main.v" $ genSource modWithTb
     runSimWithFile sim "main.v" bss
     where m = rinfo ^. mainModule
-- 
cgit