From c0c799ab3f79c370e4c33b8f824489ce8b1c96ec Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Tue, 2 Apr 2019 18:16:21 +0100 Subject: Rename to Verilog --- src/VeriFuzz/Internal/AST.hs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/VeriFuzz/Internal/AST.hs') diff --git a/src/VeriFuzz/Internal/AST.hs b/src/VeriFuzz/Internal/AST.hs index 16d40a3..49e1d30 100644 --- a/src/VeriFuzz/Internal/AST.hs +++ b/src/VeriFuzz/Internal/AST.hs @@ -34,8 +34,8 @@ setModName str = modId .~ Identifier str addModPort :: Port -> ModDecl -> ModDecl addModPort port = modInPorts %~ (:) port -addDescription :: Description -> VerilogSrc -> VerilogSrc -addDescription desc = getVerilogSrc %~ (:) desc +addDescription :: Description -> Verilog -> Verilog +addDescription desc = getVerilog %~ (:) desc testBench :: ModDecl testBench = ModDecl @@ -61,7 +61,7 @@ testBench = ModDecl ] ] -addTestBench :: VerilogSrc -> VerilogSrc +addTestBench :: Verilog -> Verilog addTestBench = addDescription $ Description testBench defaultPort :: Identifier -> Port -- cgit