From fd4b0b5152f94cd406f2e5de86ce7ed0a4d2cbd0 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Tue, 2 Apr 2019 19:47:32 +0100
Subject: Large refactor with passing tests

---
 src/VeriFuzz/Internal/AST.hs | 83 --------------------------------------------
 1 file changed, 83 deletions(-)
 delete mode 100644 src/VeriFuzz/Internal/AST.hs

(limited to 'src/VeriFuzz/Internal/AST.hs')

diff --git a/src/VeriFuzz/Internal/AST.hs b/src/VeriFuzz/Internal/AST.hs
deleted file mode 100644
index 49e1d30..0000000
--- a/src/VeriFuzz/Internal/AST.hs
+++ /dev/null
@@ -1,83 +0,0 @@
-{-|
-Module      : VeriFuzz.Internal.AST
-Description : Defaults and common functions.
-Copyright   : (c) 2018-2019, Yann Herklotz
-License     : BSD-3
-Maintainer  : ymherklotz [at] gmail [dot] com
-Stability   : experimental
-Portability : POSIX
-
-Defaults and common functions.
--}
-
-module VeriFuzz.Internal.AST where
-
-import           Control.Lens
-import           Data.Text    (Text)
-import           VeriFuzz.AST
-
-regDecl :: Identifier -> ModItem
-regDecl = Decl Nothing . Port Reg False 1
-
-wireDecl :: Identifier -> ModItem
-wireDecl = Decl Nothing . Port Wire False 1
-
--- | Create an empty module.
-emptyMod :: ModDecl
-emptyMod = ModDecl "" [] [] []
-
--- | Set a module name for a module declaration.
-setModName :: Text -> ModDecl -> ModDecl
-setModName str = modId .~ Identifier str
-
--- | Add a input port to the module declaration.
-addModPort :: Port -> ModDecl -> ModDecl
-addModPort port = modInPorts %~ (:) port
-
-addDescription :: Description -> Verilog -> Verilog
-addDescription desc = getVerilog %~ (:) desc
-
-testBench :: ModDecl
-testBench = ModDecl
-    "main"
-    []
-    []
-    [ regDecl "a"
-    , regDecl "b"
-    , wireDecl "c"
-    , ModInst "and"
-              "and_gate"
-              [ModConn $ Id "c", ModConn $ Id "a", ModConn $ Id "b"]
-    , Initial $ SeqBlock
-        [ BlockAssign . Assign (RegId "a") Nothing $ Number 1 1
-        , BlockAssign . Assign (RegId "b") Nothing $ Number 1 1
-    -- , TimeCtrl (Delay 1) . Just . SysTaskEnable $ Task "display"
-    --   [ Str "%d & %d = %d"
-    --   , PrimExpr $ PrimId "a"
-    --   , PrimExpr $ PrimId "b"
-    --   , PrimExpr $ PrimId "c"
-    --   ]
-    -- , SysTaskEnable $ Task "finish" []
-        ]
-    ]
-
-addTestBench :: Verilog -> Verilog
-addTestBench = addDescription $ Description testBench
-
-defaultPort :: Identifier -> Port
-defaultPort = Port Wire False 1
-
-portToExpr :: Port -> Expr
-portToExpr (Port _ _ _ i) = Id i
-
-modName :: ModDecl -> Text
-modName = view $ modId . getIdentifier
-
-yPort :: Identifier -> Port
-yPort = Port Wire False 90
-
-wire :: Int -> Identifier -> Port
-wire = Port Wire False
-
-reg :: Int -> Identifier -> Port
-reg = Port Reg False
-- 
cgit