From c0c799ab3f79c370e4c33b8f824489ce8b1c96ec Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Tue, 2 Apr 2019 18:16:21 +0100
Subject: Rename to Verilog

---
 src/VeriFuzz/Internal/Simulator.hs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/VeriFuzz/Internal/Simulator.hs')

diff --git a/src/VeriFuzz/Internal/Simulator.hs b/src/VeriFuzz/Internal/Simulator.hs
index 9437fab..4c21864 100644
--- a/src/VeriFuzz/Internal/Simulator.hs
+++ b/src/VeriFuzz/Internal/Simulator.hs
@@ -46,7 +46,7 @@ class (Tool a) => Synthesisor a where
            -> Sh ()    -- ^ does not return any values
 
 data SourceInfo = SourceInfo { runMainModule :: {-# UNPACK #-} !Text
-                             , runSource     :: !VerilogSrc
+                             , runSource     :: !Verilog
                              }
                   deriving (Eq, Show)
 
-- 
cgit