From c0c799ab3f79c370e4c33b8f824489ce8b1c96ec Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Tue, 2 Apr 2019 18:16:21 +0100
Subject: Rename to Verilog

---
 src/VeriFuzz/Mutate.hs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/VeriFuzz/Mutate.hs')

diff --git a/src/VeriFuzz/Mutate.hs b/src/VeriFuzz/Mutate.hs
index 4985993..1984805 100644
--- a/src/VeriFuzz/Mutate.hs
+++ b/src/VeriFuzz/Mutate.hs
@@ -67,11 +67,11 @@ nestId i m
     def = Id i
 
 -- | Replaces an identifier by a expression in all the module declaration.
-nestSource :: Identifier -> VerilogSrc -> VerilogSrc
+nestSource :: Identifier -> Verilog -> Verilog
 nestSource i src = src & getModule %~ nestId i
 
 -- | Nest variables in the format @w[0-9]*@ up to a certain number.
-nestUpTo :: Int -> VerilogSrc -> VerilogSrc
+nestUpTo :: Int -> Verilog -> Verilog
 nestUpTo i src =
     foldl (flip nestSource) src $ Identifier . fromNode <$> [1 .. i]
 
-- 
cgit