From f28188fc54d187b501b861d43592702bc7e460ec Mon Sep 17 00:00:00 2001
From: Yann Herklotz Grave <git@yannherklotzgrave.com>
Date: Sat, 16 Feb 2019 14:28:30 +0000
Subject: Add export lists

---
 src/VeriFuzz/Mutate.hs | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

(limited to 'src/VeriFuzz/Mutate.hs')

diff --git a/src/VeriFuzz/Mutate.hs b/src/VeriFuzz/Mutate.hs
index d012358..56db6c4 100644
--- a/src/VeriFuzz/Mutate.hs
+++ b/src/VeriFuzz/Mutate.hs
@@ -18,7 +18,6 @@ import           Data.Maybe        (catMaybes, fromMaybe)
 import           Data.Text         (Text)
 import qualified Data.Text         as T
 import           VeriFuzz.AST
-import           VeriFuzz.CodeGen
 import           VeriFuzz.Internal
 
 -- | Return if the 'Identifier' is in a 'ModDecl'.
@@ -74,8 +73,12 @@ nestUpTo :: Int -> VerilogSrc -> VerilogSrc
 nestUpTo i src = foldl (flip nestSource) src $ Identifier . fromNode <$> [1 .. i]
 
 allVars :: ModDecl -> [Identifier]
-allVars m = (m ^.. modOutPorts . traverse . portName) ++ (m ^.. modInPorts . traverse . portName)
+allVars m =
+  (m ^.. modOutPorts . traverse . portName)
+  <> (m ^.. modInPorts . traverse . portName)
+
 -- $setup
+-- >>> import VeriFuzz.CodeGen
 -- >>> let m = (ModDecl (Identifier "m") [Port Wire 5 (Identifier "y")] [Port Wire 5 "x"] [])
 -- >>> let main = (ModDecl "main" [] [] [])
 
-- 
cgit