From cad6bef3afe5919b987bb723cf0907cba39a000d Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Tue, 2 Apr 2019 13:04:07 +0100
Subject: Switch to Hedgehog in graph and verilog generation

---
 src/VeriFuzz/Random.hs | 11 -----------
 1 file changed, 11 deletions(-)

(limited to 'src/VeriFuzz/Random.hs')

diff --git a/src/VeriFuzz/Random.hs b/src/VeriFuzz/Random.hs
index 4330543..947f74e 100644
--- a/src/VeriFuzz/Random.hs
+++ b/src/VeriFuzz/Random.hs
@@ -59,14 +59,3 @@ randomDAG = do
 -- | Generate a random acyclic DAG with an IO instance.
 genRandomDAG :: IO Circuit
 genRandomDAG = Hog.sample randomDAG
-
--- fromGraph :: Gen ModDecl
--- fromGraph = do
---     gr <- rDupsCirc <$> Hog.resize 100 randomCircuit
---     return
---         $   initMod
---         .   head
---         $   nestUpTo 5 (generateAST gr)
---         ^.. getVerilogSrc
---         .   traverse
---         .   getDescription
-- 
cgit