From f6b7e771fd8e7bb89a3981886c93603363dd9ed2 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Fri, 8 Feb 2019 15:48:19 +0000 Subject: Add Reduce which will contain the test reduction --- src/VeriFuzz/Reduce.hs | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 src/VeriFuzz/Reduce.hs (limited to 'src/VeriFuzz/Reduce.hs') diff --git a/src/VeriFuzz/Reduce.hs b/src/VeriFuzz/Reduce.hs new file mode 100644 index 0000000..4900a67 --- /dev/null +++ b/src/VeriFuzz/Reduce.hs @@ -0,0 +1,29 @@ +{-| +Module : VeriFuzz.Reduce +Description : Test case reducer implementation. +Copyright : (c) 2019, Yann Herklotz Grave +License : GPL-3 +Maintainer : ymherklotz [at] gmail [dot] com +Stability : experimental +Portability : POSIX + +Test case reducer implementation. +-} + +module VeriFuzz.Reduce where + +import Control.Lens +import VeriFuzz.AST +import VeriFuzz.Mutate + +halve :: [a] -> ([a], [a]) +halve l = splitAt (length l `div` 2) l + +removeUninitWires :: [ModItem] -> [ModItem] +removeUninitWires ms = transformOf traverseModItem trans <$> ms + where + ids = ms ^.. traverse . modContAssign . contAssignNetLVal + +halveModDecl :: ModDecl -> (ModDecl, ModDecl) +halveModDecl m = + (m & modItems %~ fst . halve, m & modItems %~ snd . halve) -- cgit