From 186bb5f37770c150bd8e601e9761211af6a9c277 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Wed, 10 Apr 2019 23:42:58 +0100
Subject: Fix the generation of modules and add initialisation

---
 src/VeriFuzz/Sim/Icarus.hs | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/VeriFuzz/Sim/Icarus.hs')

diff --git a/src/VeriFuzz/Sim/Icarus.hs b/src/VeriFuzz/Sim/Icarus.hs
index 9b5138f..8876706 100644
--- a/src/VeriFuzz/Sim/Icarus.hs
+++ b/src/VeriFuzz/Sim/Icarus.hs
@@ -92,7 +92,8 @@ runSimIcarus sim rinfo bss = do
             [ Initial
               $  fold (addDisplay $ assignFunc (_modInPorts m) <$> bss)
               <> (SysTaskEnable $ Task "finish" [])
-            ] []
+            ]
+            []
     let newtb     = instantiateMod m tb
     let modWithTb = Verilog [newtb, m]
     writefile "main.v" $ genSource modWithTb
-- 
cgit