From 186bb5f37770c150bd8e601e9761211af6a9c277 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Wed, 10 Apr 2019 23:42:58 +0100 Subject: Fix the generation of modules and add initialisation --- src/VeriFuzz/Sim/Internal.hs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/VeriFuzz/Sim/Internal.hs') diff --git a/src/VeriFuzz/Sim/Internal.hs b/src/VeriFuzz/Sim/Internal.hs index 925b155..145042a 100644 --- a/src/VeriFuzz/Sim/Internal.hs +++ b/src/VeriFuzz/Sim/Internal.hs @@ -74,7 +74,7 @@ mainModule = lens get_ set_ set_ (SourceInfo top main) v = SourceInfo top (main & getModule %~ update top v) update top v m@(ModDecl (Identifier i) _ _ _ _) | i == top = v - | otherwise = m + | otherwise = m get_ (SourceInfo top main) = head . filter (f top) $ main ^.. getModule f top (ModDecl (Identifier i) _ _ _ _) = i == top -- cgit