From ed491e5c36e7bf298dfd969c0a222100ac532f18 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Mon, 13 May 2019 20:35:00 +0100
Subject: Add more reporting to equivalence check

---
 src/VeriFuzz/Sim/Internal.hs | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/VeriFuzz/Sim/Internal.hs')

diff --git a/src/VeriFuzz/Sim/Internal.hs b/src/VeriFuzz/Sim/Internal.hs
index 091520c..ea90122 100644
--- a/src/VeriFuzz/Sim/Internal.hs
+++ b/src/VeriFuzz/Sim/Internal.hs
@@ -74,8 +74,10 @@ class Tool a => Simulator a where
 
 data Failed = EmptyFail
             | EquivFail
+            | EquivError
             | SimFail
             | SynthFail
+            | TimeoutError
             deriving (Eq, Show)
 
 instance Semigroup Failed where
-- 
cgit