From 8f7d6e4ee2941c592a33510687a724c4c733d403 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Sun, 21 Apr 2019 07:19:06 +0100
Subject: Add new modules to fix Quartus equivalence check

---
 src/VeriFuzz/Sim/Quartus.hs | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/VeriFuzz/Sim/Quartus.hs')

diff --git a/src/VeriFuzz/Sim/Quartus.hs b/src/VeriFuzz/Sim/Quartus.hs
index 5bda0be..cac1fb8 100644
--- a/src/VeriFuzz/Sim/Quartus.hs
+++ b/src/VeriFuzz/Sim/Quartus.hs
@@ -55,6 +55,7 @@ runSynthQuartus sim (SourceInfo top src) = do
     ex (exec "quartus_eda") [top, "--simulation", "--tool=vcs"]
     liftSh $ do
         cp (fromText "simulation/vcs" </> fromText top <.> "vo") $ synthOutput sim
+        run_ "sed" ["-ri", "s,^// DATE.*,,; s,^tri1 (.*);,wire \\1 = 1;,; /^\\/\\/ +synopsys/ d;", toTextIgnore $ synthOutput sim]
         echoP "Quartus synthesis done"
   where
     inpf = "rtl.v"
-- 
cgit