From 186bb5f37770c150bd8e601e9761211af6a9c277 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Wed, 10 Apr 2019 23:42:58 +0100 Subject: Fix the generation of modules and add initialisation --- src/VeriFuzz/Sim/Reduce.hs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/VeriFuzz/Sim/Reduce.hs') diff --git a/src/VeriFuzz/Sim/Reduce.hs b/src/VeriFuzz/Sim/Reduce.hs index 5684ed5..381a84c 100644 --- a/src/VeriFuzz/Sim/Reduce.hs +++ b/src/VeriFuzz/Sim/Reduce.hs @@ -67,8 +67,8 @@ filterExpr ids (Id i) = if i `notElem` ids then Number 1 0 else Id i filterExpr _ e = e filterDecl :: [Identifier] -> ModItem -> Bool -filterDecl ids (Decl Nothing (Port _ _ _ i)) = i `elem` ids -filterDecl _ _ = True +filterDecl ids (Decl Nothing (Port _ _ _ i) _) = i `elem` ids +filterDecl _ _ = True filterAssigns :: [Port] -> ModItem -> Bool filterAssigns out (ModCA (ContAssign i _)) = -- cgit