From 02019f140184b29735bc8aca17dedb38c0a0a3f1 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Thu, 4 Apr 2019 15:29:21 +0100
Subject: Fix for latches in design

---
 src/VeriFuzz/Sim/Template.hs | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/VeriFuzz/Sim/Template.hs')

diff --git a/src/VeriFuzz/Sim/Template.hs b/src/VeriFuzz/Sim/Template.hs
index 0fc74a0..6bde792 100644
--- a/src/VeriFuzz/Sim/Template.hs
+++ b/src/VeriFuzz/Sim/Template.hs
@@ -89,6 +89,7 @@ write_verilog -force #{outf}
 sbyConfig :: (Tool a, Tool b) => FilePath -> a -> Maybe b -> SourceInfo -> Text
 sbyConfig bd sim1 sim2 (SourceInfo top src) = [st|[options]
 mode prove
+multiclock on
 
 [engines]
 smtbmc
-- 
cgit