From a3cf56b7e2edef87181c534dea099a884ac99306 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Mon, 17 Jun 2019 16:13:00 +0100
Subject: Add part of the simulator implementation

---
 src/VeriFuzz/Sim/Template.hs | 24 +++++++++++++++++++-----
 1 file changed, 19 insertions(+), 5 deletions(-)

(limited to 'src/VeriFuzz/Sim/Template.hs')

diff --git a/src/VeriFuzz/Sim/Template.hs b/src/VeriFuzz/Sim/Template.hs
index 4aa07f6..913b220 100644
--- a/src/VeriFuzz/Sim/Template.hs
+++ b/src/VeriFuzz/Sim/Template.hs
@@ -18,17 +18,19 @@ module VeriFuzz.Sim.Template
     , xstSynthConfig
     , vivadoSynthConfig
     , sbyConfig
+    , icarusTestbench
     )
 where
 
-import           Control.Lens          ((^..))
-import           Data.Text             (Text)
-import qualified Data.Text             as T
-import           Prelude               hiding (FilePath)
+import           Control.Lens             ((^..))
+import           Data.Text                (Text)
+import qualified Data.Text                as T
+import           Prelude                  hiding (FilePath)
 import           Shelly
-import           Text.Shakespeare.Text (st)
+import           Text.Shakespeare.Text    (st)
 import           VeriFuzz.Sim.Internal
 import           VeriFuzz.Verilog.AST
+import           VeriFuzz.Verilog.CodeGen
 
 rename :: Text -> [Text] -> Text
 rename end entries =
@@ -117,3 +119,15 @@ top.v
         .   fromText
         <$> deps
     readL = T.intercalate "\n" $ mappend "read -formal " <$> deps
+
+icarusTestbench :: (Synthesiser a) => Verilog -> a -> Text
+icarusTestbench t synth1 = [st|
+`include "data/cells_cmos.v"
+`include "data/cells_cyclone_v.v"
+`include "data/cells_verific.v"
+`include "data/cells_xilinx_7.v"
+`include "data/cells_yosys.v"
+`include "#{synthOutput synth1}"
+
+#{genSource t}
+|]
-- 
cgit 


From 24cf9ce5bf673615ebe36f5ab5d0ff7685dfada6 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Tue, 25 Jun 2019 22:32:21 +0100
Subject: Add back the simulation

---
 src/VeriFuzz/Sim/Template.hs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/VeriFuzz/Sim/Template.hs')

diff --git a/src/VeriFuzz/Sim/Template.hs b/src/VeriFuzz/Sim/Template.hs
index 913b220..3be6558 100644
--- a/src/VeriFuzz/Sim/Template.hs
+++ b/src/VeriFuzz/Sim/Template.hs
@@ -127,7 +127,7 @@ icarusTestbench t synth1 = [st|
 `include "data/cells_verific.v"
 `include "data/cells_xilinx_7.v"
 `include "data/cells_yosys.v"
-`include "#{synthOutput synth1}"
+`include "#{toTextIgnore $ synthOutput synth1}"
 
 #{genSource t}
 |]
-- 
cgit