From 053be2bd7b06ecb371fa0e163d4d1c3e17fe0df3 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Mon, 15 Apr 2019 20:37:15 +0100
Subject: Move declaration of SourceInfo

---
 src/VeriFuzz/Sim/Internal.hs | 20 --------------------
 src/VeriFuzz/Sim/Quartus.hs  |  1 +
 src/VeriFuzz/Sim/Reduce.hs   |  1 -
 src/VeriFuzz/Sim/Vivado.hs   |  1 +
 src/VeriFuzz/Sim/XST.hs      |  1 +
 src/VeriFuzz/Sim/Yosys.hs    |  1 +
 6 files changed, 4 insertions(+), 21 deletions(-)

(limited to 'src/VeriFuzz/Sim')

diff --git a/src/VeriFuzz/Sim/Internal.hs b/src/VeriFuzz/Sim/Internal.hs
index 3264d2e..3ff2924 100644
--- a/src/VeriFuzz/Sim/Internal.hs
+++ b/src/VeriFuzz/Sim/Internal.hs
@@ -14,8 +14,6 @@ module VeriFuzz.Sim.Internal
     ( Tool(..)
     , Simulator(..)
     , Synthesiser(..)
-    , SourceInfo(..)
-    , mainModule
     , rootPath
     , timeout
     , timeout_
@@ -27,7 +25,6 @@ module VeriFuzz.Sim.Internal
     )
 where
 
-import           Control.Lens
 import           Control.Monad         (void)
 import           Data.Bits             (shiftL)
 import           Data.ByteString       (ByteString)
@@ -63,23 +60,6 @@ class (Tool a) => Synthesiser a where
            -> FilePath -- ^ Output verilog file for the module
            -> Sh ()    -- ^ does not return any values
 
-data SourceInfo = SourceInfo { runMainModule :: {-# UNPACK #-} !Text
-                             , runSource     :: !Verilog
-                             }
-                  deriving (Eq, Show)
-
--- | May need to change this to Traversal to be safe. For now it will fail when
--- the main has not been properly set with.
-mainModule :: Lens' SourceInfo ModDecl
-mainModule = lens get_ set_
-  where
-    set_ (SourceInfo top main) v =
-        SourceInfo top (main & getModule %~ update top v)
-    update top v m@(ModDecl (Identifier i) _ _ _ _) | i == top  = v
-                                                    | otherwise = m
-    get_ (SourceInfo top main) = head . filter (f top) $ main ^.. getModule
-    f top (ModDecl (Identifier i) _ _ _ _) = i == top
-
 rootPath :: Sh FilePath
 rootPath = do
     current <- pwd
diff --git a/src/VeriFuzz/Sim/Quartus.hs b/src/VeriFuzz/Sim/Quartus.hs
index f0fbea9..13b27ae 100644
--- a/src/VeriFuzz/Sim/Quartus.hs
+++ b/src/VeriFuzz/Sim/Quartus.hs
@@ -19,6 +19,7 @@ where
 import           Prelude                  hiding (FilePath)
 import           Shelly
 import           VeriFuzz.Sim.Internal
+import           VeriFuzz.Verilog.AST
 import           VeriFuzz.Verilog.CodeGen
 
 newtype Quartus = Quartus { quartusBin :: Maybe FilePath }
diff --git a/src/VeriFuzz/Sim/Reduce.hs b/src/VeriFuzz/Sim/Reduce.hs
index 3e3b1da..6dfe757 100644
--- a/src/VeriFuzz/Sim/Reduce.hs
+++ b/src/VeriFuzz/Sim/Reduce.hs
@@ -19,7 +19,6 @@ module VeriFuzz.Sim.Reduce
 where
 
 import           Control.Lens
-import           VeriFuzz.Sim.Internal
 import           VeriFuzz.Verilog.AST
 import           VeriFuzz.Verilog.CodeGen
 import           VeriFuzz.Verilog.Mutate
diff --git a/src/VeriFuzz/Sim/Vivado.hs b/src/VeriFuzz/Sim/Vivado.hs
index 99b102c..88328a6 100644
--- a/src/VeriFuzz/Sim/Vivado.hs
+++ b/src/VeriFuzz/Sim/Vivado.hs
@@ -20,6 +20,7 @@ import           Prelude                  hiding (FilePath)
 import           Shelly
 import           VeriFuzz.Sim.Internal
 import           VeriFuzz.Sim.Template
+import           VeriFuzz.Verilog.AST
 import           VeriFuzz.Verilog.CodeGen
 
 newtype Vivado = Vivado { vivadoPath :: FilePath }
diff --git a/src/VeriFuzz/Sim/XST.hs b/src/VeriFuzz/Sim/XST.hs
index 59c897d..40bd637 100644
--- a/src/VeriFuzz/Sim/XST.hs
+++ b/src/VeriFuzz/Sim/XST.hs
@@ -23,6 +23,7 @@ import           Shelly
 import           Text.Shakespeare.Text    (st)
 import           VeriFuzz.Sim.Internal
 import           VeriFuzz.Sim.Template
+import           VeriFuzz.Verilog.AST
 import           VeriFuzz.Verilog.CodeGen
 
 data XST = XST { xstPath    :: {-# UNPACK #-} !FilePath
diff --git a/src/VeriFuzz/Sim/Yosys.hs b/src/VeriFuzz/Sim/Yosys.hs
index 4a68569..90a6ffd 100644
--- a/src/VeriFuzz/Sim/Yosys.hs
+++ b/src/VeriFuzz/Sim/Yosys.hs
@@ -26,6 +26,7 @@ import           Shelly
 import           Text.Shakespeare.Text    (st)
 import           VeriFuzz.Sim.Internal
 import           VeriFuzz.Sim.Template
+import           VeriFuzz.Verilog.AST
 import           VeriFuzz.Verilog.CodeGen
 import           VeriFuzz.Verilog.Mutate
 
-- 
cgit