From 371c28e91b6602401c3991390cb2c76fe9812e3e Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Mon, 15 Apr 2019 19:44:29 +0100
Subject: Rename Synthesisor -> Synthesiser

---
 src/VeriFuzz/Sim/Internal.hs | 8 ++++----
 src/VeriFuzz/Sim/Quartus.hs  | 2 +-
 src/VeriFuzz/Sim/Vivado.hs   | 6 +++---
 src/VeriFuzz/Sim/XST.hs      | 2 +-
 src/VeriFuzz/Sim/Yosys.hs    | 8 ++++----
 5 files changed, 13 insertions(+), 13 deletions(-)

(limited to 'src/VeriFuzz/Sim')

diff --git a/src/VeriFuzz/Sim/Internal.hs b/src/VeriFuzz/Sim/Internal.hs
index 4bfd5e9..3264d2e 100644
--- a/src/VeriFuzz/Sim/Internal.hs
+++ b/src/VeriFuzz/Sim/Internal.hs
@@ -13,7 +13,7 @@ Class of the simulator and the synthesize tool.
 module VeriFuzz.Sim.Internal
     ( Tool(..)
     , Simulator(..)
-    , Synthesisor(..)
+    , Synthesiser(..)
     , SourceInfo(..)
     , mainModule
     , rootPath
@@ -56,9 +56,9 @@ class (Tool a) => Simulator a where
                  -> [ByteString]
                  -> Sh ByteString
 
--- | Synthesisor type class.
-class (Tool a) => Synthesisor a where
-  runSynth :: a        -- ^ Synthesisor tool instance
+-- | Synthesiser type class.
+class (Tool a) => Synthesiser a where
+  runSynth :: a        -- ^ Synthesiser tool instance
            -> SourceInfo  -- ^ Run information
            -> FilePath -- ^ Output verilog file for the module
            -> Sh ()    -- ^ does not return any values
diff --git a/src/VeriFuzz/Sim/Quartus.hs b/src/VeriFuzz/Sim/Quartus.hs
index fb88047..f0fbea9 100644
--- a/src/VeriFuzz/Sim/Quartus.hs
+++ b/src/VeriFuzz/Sim/Quartus.hs
@@ -27,7 +27,7 @@ newtype Quartus = Quartus { quartusBin :: Maybe FilePath }
 instance Tool Quartus where
     toText _ = "quartus"
 
-instance Synthesisor Quartus where
+instance Synthesiser Quartus where
     runSynth = runSynthQuartus
 
 defaultQuartus :: Quartus
diff --git a/src/VeriFuzz/Sim/Vivado.hs b/src/VeriFuzz/Sim/Vivado.hs
index 0bfbd11..99b102c 100644
--- a/src/VeriFuzz/Sim/Vivado.hs
+++ b/src/VeriFuzz/Sim/Vivado.hs
@@ -1,13 +1,13 @@
 {-|
 Module      : VeriFuzz.Sim.Vivado
-Description : Vivado Synthesisor implementation.
+Description : Vivado Synthesiser implementation.
 Copyright   : (c) 2019, Yann Herklotz Grave
 License     : GPL-3
 Maintainer  : ymherklotz [at] gmail [dot] com
 Stability   : experimental
 Portability : POSIX
 
-Vivado Synthesisor implementation.
+Vivado Synthesiser implementation.
 -}
 
 module VeriFuzz.Sim.Vivado
@@ -28,7 +28,7 @@ newtype Vivado = Vivado { vivadoPath :: FilePath }
 instance Tool Vivado where
     toText _ = "vivado"
 
-instance Synthesisor Vivado where
+instance Synthesiser Vivado where
     runSynth = runSynthVivado
 
 defaultVivado :: Vivado
diff --git a/src/VeriFuzz/Sim/XST.hs b/src/VeriFuzz/Sim/XST.hs
index 026f5e7..59c897d 100644
--- a/src/VeriFuzz/Sim/XST.hs
+++ b/src/VeriFuzz/Sim/XST.hs
@@ -33,7 +33,7 @@ data XST = XST { xstPath    :: {-# UNPACK #-} !FilePath
 instance Tool XST where
     toText _ = "xst"
 
-instance Synthesisor XST where
+instance Synthesiser XST where
     runSynth = runSynthXST
 
 defaultXST :: XST
diff --git a/src/VeriFuzz/Sim/Yosys.hs b/src/VeriFuzz/Sim/Yosys.hs
index 2682fe4..4a68569 100644
--- a/src/VeriFuzz/Sim/Yosys.hs
+++ b/src/VeriFuzz/Sim/Yosys.hs
@@ -35,7 +35,7 @@ newtype Yosys = Yosys { yosysPath :: FilePath }
 instance Tool Yosys where
   toText _ = "yosys"
 
-instance Synthesisor Yosys where
+instance Synthesiser Yosys where
   runSynth = runSynthYosys
 
 defaultYosys :: Yosys
@@ -56,14 +56,14 @@ runSynthYosys sim (SourceInfo _ src) outf = do
     inp  = toTextIgnore inpf
     out  = toTextIgnore outf
 
-runMaybeSynth :: (Synthesisor a) => Maybe a -> SourceInfo -> Sh ()
+runMaybeSynth :: (Synthesiser a) => Maybe a -> SourceInfo -> Sh ()
 runMaybeSynth (Just sim) srcInfo =
     runSynth sim srcInfo $ fromText [st|syn_#{toText sim}.v|]
 runMaybeSynth Nothing (SourceInfo _ src) =
     writefile "syn_rtl.v" $ genSource src
 
 runEquivYosys
-    :: (Synthesisor a, Synthesisor b)
+    :: (Synthesiser a, Synthesiser b)
     => Yosys
     -> a
     -> Maybe b
@@ -82,7 +82,7 @@ runEquivYosys yosys sim1 sim2 srcInfo = do
         fromText [st|test.#{toText sim1}.#{maybe "rtl" toText sim2}.ys|]
 
 runEquiv
-    :: (Synthesisor a, Synthesisor b)
+    :: (Synthesiser a, Synthesiser b)
     => Yosys
     -> a
     -> Maybe b
-- 
cgit