From 4b5401ef3400413be0559dfa17718611822fc4c6 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Sat, 6 Apr 2019 21:57:48 +0100
Subject: Generate flip-flops instead of latches

---
 src/VeriFuzz/Sim/Template.hs | 1 -
 1 file changed, 1 deletion(-)

(limited to 'src/VeriFuzz/Sim')

diff --git a/src/VeriFuzz/Sim/Template.hs b/src/VeriFuzz/Sim/Template.hs
index 6bde792..0fc74a0 100644
--- a/src/VeriFuzz/Sim/Template.hs
+++ b/src/VeriFuzz/Sim/Template.hs
@@ -89,7 +89,6 @@ write_verilog -force #{outf}
 sbyConfig :: (Tool a, Tool b) => FilePath -> a -> Maybe b -> SourceInfo -> Text
 sbyConfig bd sim1 sim2 (SourceInfo top src) = [st|[options]
 mode prove
-multiclock on
 
 [engines]
 smtbmc
-- 
cgit