From 97398438902d42b33aef475e3e357781582bec16 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Thu, 18 Apr 2019 18:16:35 +0100
Subject: Add output path to each simulator

---
 src/VeriFuzz/Sim/Internal.hs | 10 ++++++----
 src/VeriFuzz/Sim/Quartus.hs  |  8 ++++++--
 src/VeriFuzz/Sim/Vivado.hs   |  8 ++++++--
 src/VeriFuzz/Sim/XST.hs      |  5 ++++-
 src/VeriFuzz/Sim/Yosys.hs    | 10 ++++++----
 5 files changed, 28 insertions(+), 13 deletions(-)

(limited to 'src/VeriFuzz/Sim')

diff --git a/src/VeriFuzz/Sim/Internal.hs b/src/VeriFuzz/Sim/Internal.hs
index 8327ad8..2d06819 100644
--- a/src/VeriFuzz/Sim/Internal.hs
+++ b/src/VeriFuzz/Sim/Internal.hs
@@ -78,10 +78,12 @@ instance Monoid Failed where
 
 -- | Synthesiser type class.
 class Tool a => Synthesiser a where
-  runSynth :: a        -- ^ Synthesiser tool instance
-           -> SourceInfo  -- ^ Run information
-           -> FilePath -- ^ Output verilog file for the module
-           -> ResultSh ()    -- ^ does not return any values
+    runSynth :: a        -- ^ Synthesiser tool instance
+             -> SourceInfo  -- ^ Run information
+             -> FilePath -- ^ Output verilog file for the module
+             -> ResultSh ()    -- ^ does not return any values
+    synthOutput :: a -> FilePath
+    setSynthOutput :: a -> FilePath -> a
 
 -- | Type synonym for a 'ResultT' that will be used throughout 'VeriFuzz'. This
 -- has instances for 'MonadSh' and 'MonadIO' if the 'Monad' it is parametrised
diff --git a/src/VeriFuzz/Sim/Quartus.hs b/src/VeriFuzz/Sim/Quartus.hs
index 0463009..beb7f10 100644
--- a/src/VeriFuzz/Sim/Quartus.hs
+++ b/src/VeriFuzz/Sim/Quartus.hs
@@ -23,7 +23,9 @@ import           VeriFuzz.Sim.Internal
 import           VeriFuzz.Verilog.AST
 import           VeriFuzz.Verilog.CodeGen
 
-newtype Quartus = Quartus { quartusBin :: Maybe FilePath }
+data Quartus = Quartus { quartusBin    :: !(Maybe FilePath)
+                       , quartusOutput :: {-# UNPACK #-} !FilePath
+                       }
                 deriving (Eq)
 
 instance Show Quartus where
@@ -34,9 +36,11 @@ instance Tool Quartus where
 
 instance Synthesiser Quartus where
     runSynth = runSynthQuartus
+    synthOutput = quartusOutput
+    setSynthOutput (Quartus a _) f = Quartus a f
 
 defaultQuartus :: Quartus
-defaultQuartus = Quartus Nothing
+defaultQuartus = Quartus Nothing "quartus/syn_quartus.v"
 
 runSynthQuartus :: Quartus -> SourceInfo -> FilePath -> ResultSh ()
 runSynthQuartus sim (SourceInfo top src) outf = do
diff --git a/src/VeriFuzz/Sim/Vivado.hs b/src/VeriFuzz/Sim/Vivado.hs
index fb43ceb..7cf6d4b 100644
--- a/src/VeriFuzz/Sim/Vivado.hs
+++ b/src/VeriFuzz/Sim/Vivado.hs
@@ -24,7 +24,9 @@ import           VeriFuzz.Sim.Template
 import           VeriFuzz.Verilog.AST
 import           VeriFuzz.Verilog.CodeGen
 
-newtype Vivado = Vivado { vivadoPath :: FilePath }
+data Vivado = Vivado { vivadoPath   :: {-# UNPACK #-} !FilePath
+                     , vivadoOutput :: {-# UNPACK #-} !FilePath
+                     }
                deriving (Eq)
 
 instance Show Vivado where
@@ -35,9 +37,11 @@ instance Tool Vivado where
 
 instance Synthesiser Vivado where
     runSynth = runSynthVivado
+    synthOutput = vivadoOutput
+    setSynthOutput (Vivado a _) f = Vivado a f
 
 defaultVivado :: Vivado
-defaultVivado = Vivado "vivado"
+defaultVivado = Vivado "vivado" "vivado/syn_vivado.v"
 
 runSynthVivado :: Vivado -> SourceInfo -> FilePath -> ResultSh ()
 runSynthVivado sim (SourceInfo top src) outf = do
diff --git a/src/VeriFuzz/Sim/XST.hs b/src/VeriFuzz/Sim/XST.hs
index 488c404..b5b1b8b 100644
--- a/src/VeriFuzz/Sim/XST.hs
+++ b/src/VeriFuzz/Sim/XST.hs
@@ -29,6 +29,7 @@ import           VeriFuzz.Verilog.CodeGen
 
 data XST = XST { xstPath    :: {-# UNPACK #-} !FilePath
                , netgenPath :: {-# UNPACK #-} !FilePath
+               , xstOutput  :: {-# UNPACK #-} !FilePath
                }
          deriving (Eq)
 
@@ -40,9 +41,11 @@ instance Tool XST where
 
 instance Synthesiser XST where
     runSynth = runSynthXST
+    synthOutput = xstOutput
+    setSynthOutput (XST a b _) f = XST a b f
 
 defaultXST :: XST
-defaultXST = XST "xst" "netgen"
+defaultXST = XST "xst" "netgen" "xst/syn_xst.v"
 
 runSynthXST :: XST -> SourceInfo -> FilePath -> ResultSh ()
 runSynthXST sim (SourceInfo top src) outf = do
diff --git a/src/VeriFuzz/Sim/Yosys.hs b/src/VeriFuzz/Sim/Yosys.hs
index 17f52df..98244a6 100644
--- a/src/VeriFuzz/Sim/Yosys.hs
+++ b/src/VeriFuzz/Sim/Yosys.hs
@@ -31,7 +31,9 @@ import           VeriFuzz.Verilog.AST
 import           VeriFuzz.Verilog.CodeGen
 import           VeriFuzz.Verilog.Mutate
 
-newtype Yosys = Yosys { yosysPath :: FilePath }
+data Yosys = Yosys { yosysPath   :: {-# UNPACK #-} !FilePath
+                   , yosysOutput :: {-# UNPACK #-} !FilePath
+                   }
               deriving (Eq)
 
 instance Tool Yosys where
@@ -39,12 +41,14 @@ instance Tool Yosys where
 
 instance Synthesiser Yosys where
   runSynth = runSynthYosys
+  synthOutput = yosysOutput
+  setSynthOutput (Yosys a _) f = Yosys a f
 
 instance Show Yosys where
     show _ = "yosys"
 
 defaultYosys :: Yosys
-defaultYosys = Yosys "yosys"
+defaultYosys = Yosys "yosys" "yosys/syn_yosys.v"
 
 runSynthYosys :: Yosys -> SourceInfo -> FilePath -> ResultSh ()
 runSynthYosys sim (SourceInfo _ src) outf = (<?> SynthFail) . liftSh $ do
@@ -112,8 +116,6 @@ runEquiv _ sim1 sim2 srcInfo = do
             $  srcInfo
             ^. mainModule
         writefile "test.sby" $ sbyConfig root sim1 sim2 srcInfo
-    runSynth sim1 srcInfo $ fromText [st|syn_#{toText sim1}.v|]
-    runMaybeSynth sim2 srcInfo
     liftSh $ echoP "SymbiYosys: run"
     execute_ EquivFail dir "symbiyosys" "sby" ["-f", "test.sby"]
     liftSh $ echoP "SymbiYosys: done"
-- 
cgit