From d13375f31f4c298a379ac3c17e7f81ea12e4312c Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Tue, 23 Apr 2019 15:51:34 +0100
Subject: Fix some errors in the templates

---
 src/VeriFuzz/Sim/Template.hs | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/VeriFuzz/Sim')

diff --git a/src/VeriFuzz/Sim/Template.hs b/src/VeriFuzz/Sim/Template.hs
index 93f24a3..771646d 100644
--- a/src/VeriFuzz/Sim/Template.hs
+++ b/src/VeriFuzz/Sim/Template.hs
@@ -90,6 +90,7 @@ write_verilog -force #{outf}
 -- brittany-disable-next-binding
 sbyConfig :: (Synthesiser a, Synthesiser b) => FilePath -> a -> Maybe b -> SourceInfo -> Text
 sbyConfig bd sim1 sim2 (SourceInfo top src) = [st|[options]
+multiclock on
 mode prove
 
 [engines]
-- 
cgit