From d695414e67f9adb7f665602a20a898fa77eba106 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Fri, 12 Apr 2019 17:16:24 +0100 Subject: Change Port type to include lower bound --- src/VeriFuzz/Sim/Reduce.hs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/VeriFuzz/Sim') diff --git a/src/VeriFuzz/Sim/Reduce.hs b/src/VeriFuzz/Sim/Reduce.hs index 381a84c..361df3e 100644 --- a/src/VeriFuzz/Sim/Reduce.hs +++ b/src/VeriFuzz/Sim/Reduce.hs @@ -67,8 +67,8 @@ filterExpr ids (Id i) = if i `notElem` ids then Number 1 0 else Id i filterExpr _ e = e filterDecl :: [Identifier] -> ModItem -> Bool -filterDecl ids (Decl Nothing (Port _ _ _ i) _) = i `elem` ids -filterDecl _ _ = True +filterDecl ids (Decl Nothing (Port _ _ _ _ i) _) = i `elem` ids +filterDecl _ _ = True filterAssigns :: [Port] -> ModItem -> Bool filterAssigns out (ModCA (ContAssign i _)) = -- cgit