From 4ba440d842e9a0502b429fbc04e2be41c8037a4c Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Sat, 19 Jan 2019 19:20:33 +0000 Subject: Add brittany formatting instead of stylish-haskell --- src/VeriFuzz/Simulator/Icarus.hs | 35 +++++++++++++++++++---------------- 1 file changed, 19 insertions(+), 16 deletions(-) (limited to 'src/VeriFuzz/Simulator/Icarus.hs') diff --git a/src/VeriFuzz/Simulator/Icarus.hs b/src/VeriFuzz/Simulator/Icarus.hs index 1f5ad38..443f096 100644 --- a/src/VeriFuzz/Simulator/Icarus.hs +++ b/src/VeriFuzz/Simulator/Icarus.hs @@ -13,12 +13,12 @@ Icarus verilog module. module VeriFuzz.Simulator.Icarus where import Control.Lens -import Data.ByteString (ByteString) -import qualified Data.ByteString as B -import Data.Foldable (fold) +import Data.ByteString ( ByteString ) +import qualified Data.ByteString as B +import Data.Foldable ( fold ) import Data.Hashable -import Data.List (transpose) -import Prelude hiding (FilePath) +import Data.List ( transpose ) +import Prelude hiding ( FilePath ) import Shelly import VeriFuzz.Simulator.General import VeriFuzz.Verilog @@ -37,26 +37,29 @@ defaultIcarus :: Icarus defaultIcarus = Icarus "iverilog" "vvp" addDisplay :: [Stmnt] -> [Stmnt] -addDisplay s = - concat $ transpose [s, replicate l $ TimeCtrl 1 Nothing - , replicate l . SysTaskEnable $ Task "display" ["%h", Id "y"]] - where - l = length s +addDisplay s = concat $ transpose + [ s + , replicate l $ TimeCtrl 1 Nothing + , replicate l . SysTaskEnable $ Task "display" ["%h", Id "y"] + ] + where l = length s assignFunc :: [Port] -> ByteString -> Stmnt assignFunc inp bs = NonBlockAssign . Assign conc Nothing . Number (B.length bs * 4) $ bsToI bs - where - conc = RegConcat (portToExpr <$> inp) + where conc = RegConcat (portToExpr <$> inp) runSimIcarus :: Icarus -> ModDecl -> [ByteString] -> Sh Int runSimIcarus sim m bss = do - let tb = ModDecl "main" [] [] - [ Initial $ - fold (addDisplay $ assignFunc (m ^. modInPorts) <$> bss) + let tb = ModDecl + "main" + [] + [] + [ Initial + $ fold (addDisplay $ assignFunc (m ^. modInPorts) <$> bss) <> (SysTaskEnable $ Task "finish" []) ] - let newtb = instantiateMod m tb + let newtb = instantiateMod m tb let modWithTb = VerilogSrc $ Description <$> [newtb, m] writefile "main.v" $ genSource modWithTb run_ (icarusPath sim) ["-o", "main", "main.v"] -- cgit