From dac34f6ff5c46f11fe6c548b92a02ebf4f10d7e9 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Thu, 10 Jan 2019 15:49:13 +0000 Subject: Rename files out of the module --- src/VeriFuzz/Simulator/Icarus.hs | 66 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) create mode 100644 src/VeriFuzz/Simulator/Icarus.hs (limited to 'src/VeriFuzz/Simulator/Icarus.hs') diff --git a/src/VeriFuzz/Simulator/Icarus.hs b/src/VeriFuzz/Simulator/Icarus.hs new file mode 100644 index 0000000..744deb8 --- /dev/null +++ b/src/VeriFuzz/Simulator/Icarus.hs @@ -0,0 +1,66 @@ +{-| +Module : VeriFuzz.Simulator.Icarus +Description : Icarus verilog module. +Copyright : (c) 2018-2019, Yann Herklotz Grave +License : BSD-3 +Maintainer : ymherklotz [at] gmail [dot] com +Stability : experimental +Portability : POSIX + +Icarus verilog module. +-} + +module VeriFuzz.Simulator.Icarus where + +import Control.Lens +import Data.ByteString (ByteString) +import qualified Data.ByteString as B +import Data.Foldable (fold) +import Data.Hashable +import Data.List (transpose) +import Data.Text (Text) +import qualified Data.Text as T +import Prelude hiding (FilePath) +import Shelly +import Text.Shakespeare.Text (st) +import VeriFuzz.Simulator.General +import VeriFuzz.Verilog + +data Icarus = Icarus { icarusPath :: FilePath + , vvpPath :: FilePath + } + +instance Simulator Icarus where + toText _ = "iverilog" + +instance Simulate Icarus where + runSim = runSimIcarus + +defaultIcarus :: Icarus +defaultIcarus = Icarus "iverilog" "vvp" + +addDisplay :: [Stmnt] -> [Stmnt] +addDisplay s = + concat $ transpose [s, replicate l $ TimeCtrl 1 Nothing + , replicate l . SysTaskEnable $ Task "display" ["%h", Id "y"]] + where + l = length s + +assignFunc :: [Port] -> ByteString -> Stmnt +assignFunc inp bs = + NonBlockAssign . Assign conc Nothing . Number (B.length bs * 4) $ bsToI bs + where + conc = RegConcat (portToExpr <$> inp) + +runSimIcarus :: Icarus -> ModDecl -> [ByteString] -> Sh Int +runSimIcarus sim m bss = do + let tb = ModDecl "main" [] [] + [ Initial $ + fold (addDisplay $ assignFunc (m ^. modInPorts) <$> bss) + <> (SysTaskEnable $ Task "finish" []) + ] + let newtb = instantiateMod m tb + let modWithTb = VerilogSrc $ Description <$> [newtb, m] + writefile "main.v" $ genSource modWithTb + run_ (icarusPath sim) ["-o", "main", "main.v"] + hash <$> run (vvpPath sim) ["main"] -- cgit