From 49291d38214cbdbf084fecc931e7e5d5732a742c Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Wed, 23 Jan 2019 19:36:18 +0000 Subject: Add echo do all the simulators --- src/VeriFuzz/Simulator/Xst.hs | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/VeriFuzz/Simulator/Xst.hs') diff --git a/src/VeriFuzz/Simulator/Xst.hs b/src/VeriFuzz/Simulator/Xst.hs index 03c1707..52272c3 100644 --- a/src/VeriFuzz/Simulator/Xst.hs +++ b/src/VeriFuzz/Simulator/Xst.hs @@ -15,8 +15,10 @@ Xst (ise) simulator implementation. module VeriFuzz.Simulator.Xst where import Control.Lens hiding ((<.>)) +import qualified Data.Text as T import Prelude hiding (FilePath) import Shelly +import System.FilePath.Posix (takeBaseName) import Text.Shakespeare.Text (st) import VeriFuzz.Simulator.General import VeriFuzz.Simulator.Internal.Template @@ -42,9 +44,12 @@ runSynthXst sim m outf = do writefile xstFile $ xstSynthConfig m writefile prjFile [st|verilog work "rtl.v"|] writefile "rtl.v" $ genSource m + echoP "Run xst" noPrint $ timeout_ (xstPath sim) ["-ifn", toTextIgnore xstFile] + echoP "Run netgen" noPrint $ run_ (netgenPath sim) ["-w", "-ofmt", "verilog", toTextIgnore $ modFile <.> "ngc", toTextIgnore outf] + echoP "Clean synthesized file" noPrint $ run_ "sed" ["-i", "/^`ifndef/,/^`endif/ d; s/ *Timestamp: .*//;", toTextIgnore outf] where modFile = fromText $ modName m -- cgit