From 49291d38214cbdbf084fecc931e7e5d5732a742c Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Wed, 23 Jan 2019 19:36:18 +0000
Subject: Add echo do all the simulators

---
 src/VeriFuzz/Simulator/Yosys.hs | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/VeriFuzz/Simulator/Yosys.hs')

diff --git a/src/VeriFuzz/Simulator/Yosys.hs b/src/VeriFuzz/Simulator/Yosys.hs
index c63d549..e18de5a 100644
--- a/src/VeriFuzz/Simulator/Yosys.hs
+++ b/src/VeriFuzz/Simulator/Yosys.hs
@@ -47,6 +47,7 @@ writeSimFile _ m file = do
 runSynthYosys :: Yosys -> ModDecl -> FilePath -> Sh ()
 runSynthYosys sim m outf = do
   writefile inpf $ genSource m
+  echoP "Run yosim"
   noPrint $ run_ (yosysPath sim) ["-q", "-b", "verilog -noattr", "-o", out, "-S", inp]
  where
   inpf = "rtl.v"
@@ -64,6 +65,7 @@ runEquivYosys yosys sim1 sim2 m = do
   writefile checkFile $ yosysSatConfig sim1 sim2 m
   runSynth sim1 m $ fromText [st|syn_#{toText sim1}.v|]
   runMaybeSynth sim2 m
+  echoP "Run yosys"
   noPrint $ run_ (yosysPath yosys) [toTextIgnore checkFile]
   where
     checkFile = fromText [st|test.#{toText sim1}.#{maybe "rtl" toText sim2}.ys|]
@@ -75,4 +77,5 @@ runEquiv yosys sim1 sim2 m = do
   writefile "test.sby" $ sbyConfig root sim1 sim2 m
   runSynth sim1 m $ fromText [st|syn_#{toText sim1}.v|]
   runMaybeSynth sim2 m
+  echoP "Run SymbiYosys"
   noPrint $ run_ "sby" ["test.sby"]
-- 
cgit