From 186bb5f37770c150bd8e601e9761211af6a9c277 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Wed, 10 Apr 2019 23:42:58 +0100
Subject: Fix the generation of modules and add initialisation

---
 src/VeriFuzz/Verilog.hs | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/VeriFuzz/Verilog.hs')

diff --git a/src/VeriFuzz/Verilog.hs b/src/VeriFuzz/Verilog.hs
index 752b754..19dc607 100644
--- a/src/VeriFuzz/Verilog.hs
+++ b/src/VeriFuzz/Verilog.hs
@@ -14,6 +14,7 @@ module VeriFuzz.Verilog
     ( Verilog(..)
     , parseVerilog
     , procedural
+    , proceduralIO
     , randomMod
     , GenVerilog(..)
     , genSource
-- 
cgit