From 1bf5b56da8df267fd33e738b53e29e832854856b Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Fri, 10 May 2019 17:41:44 +0100
Subject: Add constant expression to expression conversion and vice versa

---
 src/VeriFuzz/Verilog.hs | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/VeriFuzz/Verilog.hs')

diff --git a/src/VeriFuzz/Verilog.hs b/src/VeriFuzz/Verilog.hs
index 4f9fd52..701a7d6 100644
--- a/src/VeriFuzz/Verilog.hs
+++ b/src/VeriFuzz/Verilog.hs
@@ -53,6 +53,8 @@ module VeriFuzz.Verilog
     -- * Expression
     , Expr(..)
     , ConstExpr(..)
+    , constToExpr
+    , exprToConst
     , constNum
     -- * Assignment
     , Assign(..)
-- 
cgit