From 1f92f329dabfaf5077bed677a273a196667229e1 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Fri, 26 Apr 2019 13:48:32 +0100
Subject: Add random bit selection for wires

This has not been tested fully yet
---
 src/VeriFuzz/Verilog/AST.hs | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/VeriFuzz/Verilog/AST.hs')

diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs
index f122214..ea7ef1b 100644
--- a/src/VeriFuzz/Verilog/AST.hs
+++ b/src/VeriFuzz/Verilog/AST.hs
@@ -209,6 +209,8 @@ data UnaryOperator = UnPlus    -- ^ @+@
 data Expr = Number {-# UNPACK #-} !BitVec
           -- ^ Number implementation containing the size and the value itself
           | Id {-# UNPACK #-} !Identifier
+          | VecSelect {-# UNPACK #-} !Identifier !Expr
+          | RangeSelect {-# UNPACK #-} !Identifier !Range
           -- ^ Symbols
           | Concat ![Expr]
           -- ^ Bit-wise concatenation of expressions represented by braces.
-- 
cgit